A novel CDP DS/SS system with 2-dimensional Ikeda map chaotic sequence

Implementation of Direct Sequence Spread Spectrum Communication System Using FPGA

“…In the detection phase, the control circuit resets ld=0 and run=0. During this phase the received data of 256 bits are loaded into the upper 8 registers of detector, each register with 32-bits and is compared with the bit pattern which is already stored in the lower 8 registers of the detector [26].…”