A novel architecture for a high-performance network processing unit: Flexibility at multiple levels of abstraction

Hauger, Simon

doi:10.1109/hpsr.2009.5307421

Cited by 2 publications

(3 citation statements)

References 9 publications

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“…A slow path general-purpose processor, located on a second FPGA, performs control and management tasks. As stated in [4], software-level modules can only process a packet for N ·F clock cycles, with N parallel processors with an F times higher clock frequency than the system pipeline. Hence, we designed small, specialized RISC-cores with an instruction set similar to that of the Intel (now Netronome) IXP2xxx microengines [6].…”

Section: Prototype and Evaluationmentioning

confidence: 99%

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Designing high-speed packet processing tasks at arbitrary levels of abstraction

Hauger

2009

Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems

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Packet processing systems of forthcoming high-speed network nodes demand extremely high processing rates, but also modularity and easy adaptability due to new or evolving protocols and services. As the fixed architecture and instruction set of current network processors sometimes hinders an efficient implementation of processing tasks, we introduced the MIXMAP architecture [4] that is designed to offer programmability at multiple levels of abstraction. Now we describe the prototypical realization of this architecture showing its feasibility. Our results indicate that up to 170 million packets per second can be processed with this architecture using current FPGAs. By implementing packet processing tasks at register-transfer level and at software level, we validate the architecture's applicability and the benefits of implementing at an appropriate level of abstraction.

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Section: Prototype and Evaluationmentioning

confidence: 99%

“…In [4] we presented a novel architecture for a high-performance network processing unit, called MIXMAP. It provides a framework for modules that are programmed at different levels of abstraction.…”

Section: Introductionmentioning

confidence: 99%

Designing high-speed packet processing tasks at arbitrary levels of abstraction

Hauger

2009

Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems

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“…The Quick-Start module needs only 4.5 ns, due to its lower processing demands. Within a fully working Internet Router design [22] additional interconnection delays result in a reduced performance. With a processing time of 6 ns per packet, the Quick-Start module is capable to process 165 Mpps-being sufficient for a 100 Gbps Ethernet line card.…”

Section: Realization Using Programmable Logicmentioning

confidence: 99%

Evaluation of Router Implementations for Explicit Congestion Control Schemes

Hauger¹,

Scharf²,

Kögel³

et al. 2010

JCM

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Explicit congestion control schemes use router feedback to overcome limitations of the standard mechanisms of the Transmission Control Protocol (TCP). These approaches require additional packet processing in every router and therefore raise the question whether, and how, this can be achieved in high-speed routers. This paper investigates the realization complexity of these router functions of two such schemes, the TCP Quick-Start extension and the Explicit Control Protocol (XCP). Our focus lies on the implementation using a network processor. We show that synchronization issues among parallel processing entities have to be considered, and that this affects the router performance. We develop and compare different synchronization mechanisms for highly parallel packet processing. Our prototype implementation on an Intel IXP network processor allows to quantify the impact on throughput and delay caused by the additional packet processing in the fast path. The measurements reveal that Quick-Start and XCP processing is feasible at multiple Gbit/s line speed, with Quick-Start being simpler to scale. We expect similar results for the implementation of the Rate Control Protocol (RCP), which is another router-assisted congestion control scheme, requiring no elaborate synchronization. Finally, we study the implementation using programmable logic and show the applicability of XCP and in particular Quick-Start even at significantly higher line speeds.

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A novel architecture for a high-performance network processing unit: Flexibility at multiple levels of abstraction

Cited by 2 publications

References 9 publications

Designing high-speed packet processing tasks at arbitrary levels of abstraction

Designing high-speed packet processing tasks at arbitrary levels of abstraction

Evaluation of Router Implementations for Explicit Congestion Control Schemes

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