Abstract:Scaling silicon germanium heterojunction bipolar transistors (SiGe HBTs) to attain simultaneous increases in the figures of merit, fT
and fMAX
has necessitated a deep understanding of the inherent features of the process as it relates to the final device performance. Layout variations in the location of the field polysilicon layer relative to the edge of the active silicon region, results in marked changes in the intrinsic device, with increases in fT/fMAX
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