A novel approach to cache block reuse predictions

Jalminger, Jonas; Stenström, Per

doi:10.1109/icpp.2003.1240592

Cited by 26 publications

(19 citation statements)

References 10 publications

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“…Bypassing: Prior work has also used bypassing [6], [10], [11], [22], [27] to improve cache efficiency. Tyson et al proposed bypassing based on the hit rate of the missing load/store instruction [27].…”

Section: Prior Work On Dead Block Predictionmentioning

confidence: 99%

Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency

Liu

Ferdman

Huh

et al. 2008

2008 41st IEEE/ACM International Symposium on Microarchitecture

163

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Data caches in general-purpose microprocessors often contain mostly dead blocks and are thus used inefficiently. To improve cache efficiency, dead blocks should be identified and evicted early. Prior schemes predict the death of a block immediately after it is accessed; however, these schemes yield lower prediction accuracy and coverage. Instead, we find that predicting the death of a block when it just moves out of the MRU position gives the best tradeoff between timeliness and prediction accuracy/coverage. Furthermore, the individual reference history of a block in the L1 cache can be irregular because of data/control dependence. This paper proposes a new class of dead-block predictors that predict dead blocks based on bursts of accesses to a cache block. A cache burst begins when a block becomes MRU and ends when it becomes non-MRU. Cache bursts are more predictable than individual references because they hide the irregularity of individual references. When used at the L1 cache, the best burst-based predictor can identify 96% of the dead blocks with a 96% accuracy. With the improved dead-block predictors, we evaluate three ways to increase cache efficiency by eliminating dead blocks early: replacement optimization, bypassing, and prefetching. The most effective approach, prefetching into dead blocks, increases the average L1 efficiency from 8% to 17% and the L2 efficiency from 17% to 27%. This increased cache efficiency translates into higher overall performance: prefetching into dead blocks outperforms the same prefetch scheme without dead-block prediction by 12% at the L1 and by 13% at the L2.

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Section: Prior Work On Dead Block Predictionmentioning

confidence: 99%

Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency

Liu

Ferdman

Huh

et al. 2008

2008 41st IEEE/ACM International Symposium on Microarchitecture

163

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“…Karlsson and Hagersten found that the number of cache replacements between a block's last use and its eviction is fairly stable, and checked whether a block's reuse distance is smaller [10]. Jalminger and Stenström targeted similar goals using a structure similar to a two level branch predictor [7]. In a different approach, Tyson et al implemented non-transiency prediction by identifying load/store operations that are likely to cause a cache miss, using a cache bypass for the fetched data [15].…”

Section: Identifying the Core Working Setmentioning

confidence: 99%

Probabilistic Prediction of Temporal Locality

Etsion

Feitelson

2007

IEEE Comput. Arch. Lett.

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Abstract-The increasing gap between processor and memory speeds, as well as the introduction of multi-core CPUs, have exacerbated the dependency of CPU performance on the memory subsystem. This trend motivates the search for more efficient caching mechanisms, enabling both faster service of frequently used blocks and decreased power consumption. In this paper we describe a novel, random sampling based predictor that can distinguish transient cache insertions from non-transient ones. We show that this predictor can identify a small set of data cache resident blocks that service most of the memory references, thus serving as a building block for new cache designs and block replacement policies. Although we only discuss the L1 data cache, we have found this predictor to be efficient also when handling L1 instruction caches and shared L2 caches.

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“…A number of works focus on predicting which data will be reused using predictors and information collected based on either the program counter (PC) [2,4,5] or the address [6,7,8].…”

Section: Related Workmentioning

confidence: 99%

“…Instructions which create a lot of misses are not allowed to allocate, identified by a two-bit predictor; later used in [7] to predict which data should be bypassed based on addresses instead of PC. Similarly, Johnson et al [6] store counters in Memory Access Table, looked up to decide bypassing.…”

Section: Related Workmentioning

confidence: 99%

Applying SVM to data bypass prediction in multi core last-level caches

Sritriratanarak

Ekpanyapong

Chongstitvatana

2015

IEICE Electron. Express

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Bypassing emerged as a performance improvement method for shared Last-Level Caches (LLC) in multicore processors where large data portions are never reused, wasting system resources. This paper proposes an alternative method to predict data bypassing using Support Vector Machine (SVM). Based on access traces obtained from a simulator, SVM is trained to generate bypass models which are integrated into the simulator to quantify LLC performance improvements. Results show that SVM can classify which data to bypass, improving LLC performance, achieving an average 6.72% miss rate decrease across SPLASH2 benchmark combinations.

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A novel approach to cache block reuse predictions

Cited by 26 publications

References 10 publications

Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency

Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency

Probabilistic Prediction of Temporal Locality

Applying SVM to data bypass prediction in multi core last-level caches

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