A novel approach for leakage power reduction in deep submicron technologies in CMOS VLSI circuits

Dadoria, Ajay Kumar; Khare, Kavita; Singh, Reena

doi:10.1109/ic4.2015.7375536

Cited by 6 publications

(4 citation statements)

References 11 publications

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“…Today, we are considering complex chips comprising high level of power dissipation plus generated heat, and therefore need to be in line with the reduction in the dimensions of microelectronics and digital devices. Currently, commercial microprocessor circuits are available with CMOS transistors with a lateral size in Nano-meter process technology, such miniaturization has led to enormous power and temperature challenges with the presence of billions of transistors on the chip [1,2]. Higher power dissipation leads to increase chip temperature levels that compromising the life of microprocessors due to the addition of new features and performance.…”

Section: Introductionmentioning

confidence: 99%

Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

Sulaiman¹

2020

IJECE

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The progress of microelectronics making possible higher integration densities, and a considerable development of on-board systems are currently undergoing, this growth comes up against a limiting factor of power dissipation. Higher power dissipation will cause an immediate spread of generated heat which causes thermal problems. Consequently, the system's total consumed energy will increase as the system temperature increase. High temperatures in microprocessors and large thermal energy of computer systems produce huge problems of system confidence, performance, and cooling expenses. Power consumed by processors are mainly due to the increase in number of cores and the clock frequency, which is dissipated in the form of heat and causes thermal challenges for chip designers. As the microprocessor’s performance has increased remarkably in Nano-meter technology, power dissipation is becoming non-negligible. To solve this problem, this article addresses power dissipation reduction issues for high performance processors using multi-objective Pareto front (PF), and particle swarm optimization (PSO) algorithms to achieve power dissipation as a prior computation that reduces the real delay of a target microprocessor unit. Simulation is verified the conceptual fundamentals and optimization of joint body and supply voltages (Vth-VDD) which showing satisfactory findings.

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Section: Introductionmentioning

confidence: 99%

Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

Sulaiman¹

2020

IJECE

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“…According to [Dadoria, Khare and Singh 2015], the leakage power corresponds to approximately 45% of the total power consumption in ICs designed using a 90nm technology.…”

Section: Introductionmentioning

confidence: 99%

Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

Placido

Reis

2019

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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The shrink of the devices sizes allows the number of transistors in the integrated circuits to grow, leading to an increase in the leakage power. The discrete gate sizing technique consists in assigning each gate of the circuit to a cell option among the implementation versions available in the cell library. It is a powerful method used in the design flow to carry out optimizations, e.g., timing violations fixing and power and/or area minimization. The Lagrangian relaxation based gate sizer proposed in [Flach et al. 2013] has the best leakage power results published so far for the 2012 ISPD Gate Sizing Contest benchmarks. However, its Lagrangian relaxation phase has some drawbacks. It requires many iterations to converge to a good solution in terms of leakage power. Also, during the initial iterations, the leakage power blows up, so a parcel of the iterations is used to reduce this peak of leakage power. Yet, the Lagrangian relaxation subproblem solver does not rely on any technique to perform cell option candidate filtering, so it can be very timing consuming. Therefore, in this work, the discrete gate sizing flow proposed in [Flach et al. 2013] is extended to tackle the drawbacks aforementioned. It is proposed some enhancements to the Lagrange multiplier update formula that enable the Lagrangian relaxation core to converge faster. It is also used a scaling factor to properly scale timing cost and leakage power when evaluating a cell candidate in the Lagrangian relaxation subproblem solver. So, the scaling factor, alongside the new Lagrange multipliers update method, controls the leakage power blow up during the initial Lagrangian relaxation iterations. Moreover, it is applied a cell option candidate filtering strategy to reduce the runtime of each Lagrangian relaxation iteration. Finally, the post-processing timing recovery and power recovery phases of the original work are improved to reduce the overall flow runtime. The new approach achieved leakage power results similar to the baseline work, taking 4.28× fewer iterations and 9.11× fewer cell option candidates evaluation, on average, in the Lagrangian relaxation phase. Also, the leakage power blow up during the initial iterations of the Lagrangian relaxation was reduced from 9.55× the final value, on average, to 2.74× the final value, on average. Finally, compared to [Sharma et al. 2017], which is the fastest gate sizing algorithm published so far, the new approach produced, without using the post-processing power recovery phase, similar leakage power results in general, performing slightly better for the largest benchmark.

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“…However, switching of repeaters itself adds to total delay and also contributes to power loss . Buffers may consume power even when they are not switching . Thus, an imperative need arises to design smart buffers or repeaters which assist in boosting the speed of interconnects without compromising on dynamic as well as static power saving.…”

Section: Introductionmentioning

confidence: 99%

Designing of ultra‐low‐power high‐speed repeaters for performance optimization of VLSI interconnects at 32 nm

Khursheed

Khare

Haque

2018

Int J Numerical Modelling

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This paper resolves the performance issue encountered in very-large-scale integration interconnects due to downsizing of integrated circuits. Interconnects designed using carbon nanotubes (CNT) are compared with conventional copper interconnect. The propagation delay of very lengthy interconnect wires is ameliorated by interpolating smart buffers as repeaters within the wires.Existing buffer designs are contrived using both CNT and MOS technology for comparison using a different combination of MOS repeater-Cu interconnect and CNT repeater-CNT interconnect. Propound buffer uses power gating techniques and automated toggling approach to reduce delay besides mitigating average power consumption. Compared to conventional buffer, PropoundDesign3 brings about dynamic power saving of 99.94% and leakage power saving of 93%, but causes delay penalty. PropoundDesign2 saves dynamic power by 99.86% and leakage power by 88% and offers reduction in delay by 52%. Whereas PropoundDesign1 saves dynamic power by 98% and reduces propagation delay by 64% but on the cost of leakage power consumption. Simulation for 32 nm is done in HSPICE by considering a section of long interconnect line as driver interconnect load system using Stanford SPICE model for CNT and BSIM4 PTM for MOS.

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A novel approach for leakage power reduction in deep submicron technologies in CMOS VLSI circuits

Cited by 6 publications

References 11 publications

Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

Designing of ultra‐low‐power high‐speed repeaters for performance optimization of VLSI interconnects at 32 nm

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