A novel approach for designing GaAs FET frequency multipliers with optimum conversion gain and power efficiency

Abstract

This article reports a new experimental design technique for GaAs FET frequency multipliers based on harmonic load‐pull measurements [1]. The choices of biasing point, input power level, and load impedances at the fundamental and harmonic frequencies are examined to optimize the conversion gain and the multiplier power efficiency. This technique was validated by designing a 2.5–7.5‐GHz frequency tripler, using the NE 71083 GaAs FET. The performance of the frequency tripler built in MIC technology was found comparable to the multiharmonic load‐pull results and simulation results. © 1992 John Wiley & Sons, Inc.

Six-port-based active source-pull measurement technique

“…It is also possible to control the load impedances seen at each output frequency independently by combining separated active load-pull signals [5]. These abilities allow the design of nonlinear circuitry such as FET frequency multipliers, FET oscillators and power amplifiers with higher performance [6,7].…”