A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing

Furukawa, Hiroshi; Wen, Xiaoqing; Wang, Laung-terng; Sheu, Boryau; Jiang, Zhigang; Wu, Shianling

doi:10.1109/test.2006.297641

Cited by 18 publications

(4 citation statements)

References 18 publications

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“…4(a) and 4(b), should be able to be generated for at-speed testing of the inter-clock-domain logic. In order to generate these waveforms, the existing methods have timely performed clock gating, considering the timing relation between two different clocks [18][19][20][21][22]. They adjusted clock gating enable timing using a delay control register or a shift register to make the launch clock pulse in a clock domain and the capture clock pulse in the other clock domain.…”

Section: Related Workmentioning

confidence: 99%

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

Yi¹

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-onchip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

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Section: Related Workmentioning

confidence: 99%

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

Yi¹

2013

JSTS:Journal of Semiconductor Technology and Science

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“…The dotted clock pulses shown in the figure indicate the suppressed capture pulses. As this method requires a much more complex timing-control diagram, a clock suppression circuit similar to those proposed in Beck et al [2005], Fan et al [2007], Furukawa et al [2006], and Keller et al [2007] is needed to enable or disable the selected capture pulses. The dotted clock pulses shown in the figure indicate the suppressed capture pulses.…”

Section: Aligned Launch-on-shift For Synchronous Domainsmentioning

confidence: 99%

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Wang

Wen

et al. 2012

ACM Trans. Des. Autom. Electron. Syst.

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This article presents a hybrid Automatic Test Pattern Generation (ATPG) technique using the staggered Launch-On-Shift (LOS) scheme followed by the one-hot launch-on-shift scheme for testing delay faults in a scan design containing asynchronous clock domains. Typically, the staggered scheme produces small test sets but needs long ATPG runtime, whereas the one-hot scheme takes short ATPG runtime but yields large test sets. The proposed hybrid technique is intended to reduce test pattern count with acceptable ATPG runtime for multimillion-gate scan designs. In case the scan design contains multiple synchronous clock domains, and each group of synchronous clock domains is treated as a clock group and tested using a launch-aligned or a capture-aligned LOS scheme. By combining these schemes together, we found the pattern counts for two large industrial designs were reduced by approximately 1.6X to 1.8X, while the ATPG runtime was increased by 40% to 50%, when compared to the one-hot clocking scheme alone.

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“…Compared with other designs that using on-chip clock for at-speed testing [15,16] , our design is much simpler, and easy to extend to providing more flexible test sequences in various designs for multi-clock domains testing. Based on this PCC unit, we further presented a clock control scheme to test timing-related faults in inter-clock domain and intra-clock domain logics in [17].…”

Section: Pll Clock Control (Pcc) Unitmentioning

confidence: 99%

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

Wang

et al. 2008

J. Comput. Sci. Technol.

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HW et al. Design-for-testability features and test implementation of a giga hertz general purposeAbstract This paper describes the design-for-testability (DFT) features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test (BIST) circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops (PLL) to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation (ATPG) and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing (HVM) DFT plan to meet high quality test goals as well as slow test power consumption and cost.

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A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing

Cited by 18 publications

References 18 publications

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

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