2006
DOI: 10.1109/test.2006.297641
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A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing

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Cited by 18 publications
(4 citation statements)
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“…4(a) and 4(b), should be able to be generated for at-speed testing of the inter-clock-domain logic. In order to generate these waveforms, the existing methods have timely performed clock gating, considering the timing relation between two different clocks [18][19][20][21][22]. They adjusted clock gating enable timing using a delay control register or a shift register to make the launch clock pulse in a clock domain and the capture clock pulse in the other clock domain.…”
Section: Related Workmentioning
confidence: 99%
“…4(a) and 4(b), should be able to be generated for at-speed testing of the inter-clock-domain logic. In order to generate these waveforms, the existing methods have timely performed clock gating, considering the timing relation between two different clocks [18][19][20][21][22]. They adjusted clock gating enable timing using a delay control register or a shift register to make the launch clock pulse in a clock domain and the capture clock pulse in the other clock domain.…”
Section: Related Workmentioning
confidence: 99%
“…The dotted clock pulses shown in the figure indicate the suppressed capture pulses. As this method requires a much more complex timing-control diagram, a clock suppression circuit similar to those proposed in Beck et al [2005], Fan et al [2007], Furukawa et al [2006], and Keller et al [2007] is needed to enable or disable the selected capture pulses. The dotted clock pulses shown in the figure indicate the suppressed capture pulses.…”
Section: Aligned Launch-on-shift For Synchronous Domainsmentioning
confidence: 99%
“…Compared with other designs that using on-chip clock for at-speed testing [15,16] , our design is much simpler, and easy to extend to providing more flexible test sequences in various designs for multi-clock domains testing. Based on this PCC unit, we further presented a clock control scheme to test timing-related faults in inter-clock domain and intra-clock domain logics in [17].…”
Section: Pll Clock Control (Pcc) Unitmentioning
confidence: 99%