A novel and efficient method to initialize FPGA embedded memory content in asymptotically constant time

Bartík, Matěj; Ubik, Sven; Kubalik, Pavel

doi:10.1109/reconfig.2016.7857146

Cited by 2 publications

(14 citation statements)

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“…The time (latency) required for transferring the processed data to/from input/output buffers has the same lower bound asymptotic complexity as the compression itself, the Ω(n). The question is, which compression dictionary architecture can match or decrease such lower bound asymptotic complexity, especially when the required dictionary can be larger than the buffers [5]?…”

Section: Discussionmentioning

confidence: 99%

“…On the other hand, no current architecture has emphasized lowering an architecture overhead to reduce the respective architecture computation latency or resource utilization. It has been identified [5] that the overhead (a compression dictionary initialization) necessary for the compression process (computation phase) could require more time than the compression itself.…”

Section: Brief Motivation and Contributionsmentioning

confidence: 99%

“…• We analyzed three existing techniques suitable for implementing a compression algorithm dictionary, including our new technique [5]. • We created a new methodology for evaluating the analyzed techniques.…”

Section: Brief Motivation and Contributionsmentioning

confidence: 99%

“…The size (and the architecture) of the dictionary has a great influence on the compression ratio. A larger or better organized dictionary improves the compression ratio of the implemented compression algorithm because of the increased probability of finding a match over the larger sliding window [5].…”

Section: A Lz77 Principles and The Impact Of The Dictionarymentioning

confidence: 99%

“…We proposed an approach [5], [54] that combines previous approaches to get as many advantages (like the same asymptotic complexity [51] requiring less FPGA resources than the flip flop based approach) and to mitigate as many FIGURE 3. Architecture of the "Elementary Block".…”

Section: Distributed Memory Based Approach For a Status Registermentioning

confidence: 99%

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An In-Sight Into How Compression Dictionary Architecture Can Affect the Overall Performance in FPGAs

2020

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This paper presents a detailed analysis of various approaches to hardware implemented compression algorithm dictionaries, including our optimized method. To obtain comprehensive and detailed results, we introduced a method for the fair comparison of programmable hardware architectures to show the benefits of our approach from the perspective of logic resources, frequency, and latency. We compared two generally used methods with our optimized method, which was found to be more suitable for maintaining the memory content via (in)valid bits in any mid-density memory structures, which are implemented in programmable hardware such as FPGAs (Field Programmable Gate Array). The benefits of our new method based on a "Distributed Memory" technique are shown on a particular example of compression dictionary but the method is also suitable for another use cases requiring a fast (re-)initialization of the used memory structures before each run of an algorithm with minimum time and logic resources consumption. The performance evaluation of the respective approaches has been made in Xilinx ISE and Xilinx Vivado toolkits for the Virtex-7 FPGA family. However the proposed approach is compatible with 99% of modern FPGAs.

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Section: Discussionmentioning

confidence: 99%

Section: Brief Motivation and Contributionsmentioning

confidence: 99%

Section: Brief Motivation and Contributionsmentioning

confidence: 99%

Section: A Lz77 Principles and The Impact Of The Dictionarymentioning

confidence: 99%

Section: Distributed Memory Based Approach For a Status Registermentioning

confidence: 99%

See 3 more Smart Citations