A Novel Aging Monitoring Circuit

Abstract

Year by year there are numerous new requirements set to the lifetime and reliability of integrated circuits (IC), particularly in medical spheres and automotive applications. Consistent with technology downscaling the device reliability issues are increasing, but the quality requirements become stronger. Nowadays the aging phenomenon is one of the critical issues in systems with longer lifetime. Therefore, the monitoring of aging and its consequence compensation have become one of the key parts for today’s ICs. A novel aging monitoring circuit is proposed in this paper. This new monitoring circuit monitors the aging degradation during lifetime of the IC and generates a binary co¬d¬e. This code is applied to the inputs of compensation circuits, which compensates the degrad¬ati¬on in the critical blocks throughout their lifetime. Monitoring circuit is realized with a 14 nm technology node and simulations proved the results’ validity.