A novel adiabatic SRAM cell implementation using split level charge recovery logic

Abstract

With the advancement in technologies, data storage has become crucial for low power applications. Static random access memory (SRAM) is popular for its fast access of data but it is prone to high power dissipation. Adiabatic logic is one of the techniques which have proven to reduce the energy consumed by the circuit per operation. A novel adiabatic SRAM cell has been proposed in this paper. The proposed cell resembles the operation of the conventional 6T SRAM cell. The latch of the SRAM cell has been modelled using split level charge recovery logic (SCRL). The proposed circuit is simulated using Cadence Virtuoso (180nm) and it is compared with the conventional 6T SRAM cell. The proposed SRAM cell consumes 8.7 times less power as compared to the conventional 6T SRAM cell at 100MHz.

Low‐power and high‐speed 13T SRAM cell using FinFETs

“…The pull-up network is connected to reduced power supply (V dd /2) during the data retention phase as the sleep signal is activated that thereby reduces the leakage power of the circuit. The power gating techniques are used to reduce the power consumption of the circuit by reducing the power wastage during the undesired phases of the circuit operation [17][18][19]. Here, the sleep transistor is switched ON during the hold mode of the SRAM design.…”