The full-text may be used and/or reproduced, and given to third parties in any format or medium, without prior permission or charge, for personal research or study, educational, or not-for-prot purposes provided that:• a full bibliographic reference is made to the original source • a link is made to the metadata record in DRO • the full-text is not changed in any way The full-text must not be sold in any format or medium without the formal permission of the copyright holders.Please consult the full DRO policy for further details. Abstract. We propose in this paper an algebraic approach to hardware/software partitioning in Verilog HDL. We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntaxbased algebraic rules to conduct hardware/software partitioning. The cospecification language and the target hardware and software description languages are specific subsets of Verilog, which brings forth our successful verification for the correctness of the partitioning process by algebra of Verilog. Facilitated by Verilog's rich features, we have also successfully studied hw/sw partitioning for environment-driven systems.