A nonparametric Bayes approach to decide system burn-in time

Traditionally, to assess reliability lifetimes and to evaluate reliability performance of semiconductor devices and chips, we test the samples to their failures. This can be called the "Test-to-Fail" scenario, which usually takes a long time (e.g., longer than a week). The Test-to-Failure scenario is required especially at the qualification stage, whose objective is to obtain the lifetimes of, e.g., devices, dielectrics, and metal lines. Due to the long test times, this approach is inadequate for reliability monitors, which need to be completed in a much shorter period of time so the product shipment will not be delayed and, if failed, timely corrective actions can be taken. Therefore, we are in urgent need of a much more efficient method to judge if the monitor meets reliability requirements. The "Test-to-Target" reliability test methodology perfectly matches such demand by only stressing the samples to much shorter times and can be applied on most common reliability tests like NBTI (Negative Bias Temperature Instabilities), HCI (Hot Carrier Injection), TDDB (Time Dependent Dielectric Breakdown), Isothermal EM test, and IMD (Inter Metal Dielectric) V ramp test. The corresponding specs for the Test-toTarget approach are defined based on the baseline records from the former complete Test-to-Fail reliability tests. From practical exercises after a long time, we prove the Test-to-Target methodology a truly useful approach particularly effective for reliability monitors, inline reliability assessments, process change management, nonconformance dispositions, and tool releases.

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“…More samples tested implies a higher confidence level can be achieved to guarantee a lower ppm level as shown in Eq. (15):…”

Section: Saving On Test Time and Test Resourcementioning

confidence: 99%

The Test-to-Target Methodologies for the Risk Assessment of Semiconductor Reliability

Chien

Atman

Chang

et al. 2013

Int. J. Rel. Qual. Saf. Eng.

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“…By Eq. (1), given the bum-rn time to be x, the failure rate (in FIT, i09 device-hour) of a product after releasing for field use for y-hr is io ( F(x Acc+y) _F(xAcc) )/ y = i09 (exp(-(x Acc/a)) -exp(-((x Acc + y)/a)) )/ y (2) where Acc is the acceleration factor. The Acc is usually derived by multiplying the temperature (At) and voltage acceleration (Av) effect.…”

Section: Time Tmentioning

confidence: 99%

<title>Burn-in strategy based on Weibull failures</title>

Chien¹,

Huang²

2000

SPIE Proceedings

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Bum-rn is crucial for IC's, especially for DRAM. To meet the target failure rate after releasing the products to customers, the manufacturers have to bum-in the chips after assembly and FT (Final Test) for a certain period oftime to weed-out the weaker parts. It is important to determine the bum-in time and to set-up a re-bum-in strategy to meet required failure rate and to maintain cost-effective at the same time. This paper introduces an innovative approach to achieve these two objectives along with some practical concerns on burn-in at field applications. The proposed methodology can be applied on versatile statistical distributions. In this presentation, the selected failure mechanism follows Weibull distribution to illustrate our approaches.

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Semiconductor Device Manufacture Yield and Reliability Modeling

Kuo

Kim

1999

Wiley Encyclopedia of Electrical and Electronics Engineering

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The sections in this article are Burn‐In of Semiconductors Modeling Yield Cost Factors Fault Coverage and Occurrence Yield–Reliability Relation Models Conclusions Acknowledgments

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A nonparametric Bayes approach to decide system burn-in time

Cited by 11 publications

References 9 publications

The Test-to-Target Methodologies for the Risk Assessment of Semiconductor Reliability

The Test-to-Target Methodologies for the Risk Assessment of Semiconductor Reliability

<title>Burn-in strategy based on Weibull failures</title>

Semiconductor Device Manufacture Yield and Reliability Modeling

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