A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities

Chen, Ying-Yen; Liou, Jing-Jia

doi:10.1109/ats.2009.32

Cited by 14 publications

(9 citation statements)

References 26 publications

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“…An example of three segments is shown in Fig.2. For the serial connection, the expected delay of each segment is portioned out the expected value of the whole path-delay according to the ratio of their variations [5], [6]. For the case in Fig.2, the delay values of segment 1, 2, and 3 are denoted as x 1 , x 2 , and x 3 , and their standard deviations as σ 1 , σ 2 , and σ 3 , respectively.…”

Section: A Serial Connectionmentioning

confidence: 99%

Delay analysis of sub-path on fabricated chips by several path-delay tests

Takanobu

Takashima

Nakamura

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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We propose a method to analysis the delay of the sub-path on fabricated chips by the several path-delay tests. In recent years, the process variation causes the timing faults. To detect the faults, the path-delay test is one of the most promising methods. The path-delay test checks whether the signals along the target paths in fabricated LSIs are propagated under the specified frequency. In this paper, we propose a method to analysis the delay value of the paths with path-delay tests. The proposed method consists of 1) path-delay tests for several paths, 2) estimation of the sub-path of the testing paths, and 3) expansion of the remaining path according to the resultant estimations. We confirm that our proposed method calculates the delay with about 0.05% errors empirically.

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Section: A Serial Connectionmentioning

confidence: 99%

Delay analysis of sub-path on fabricated chips by several path-delay tests

Takanobu

Takashima

Nakamura

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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“…In post-silicon debug stage, we can validate timing libraries by comparing measured segment delays and the gate or wire delays in the timing model [7]. During manufacturing, we can locate defective segments for faulty chips and perform physical failure analysis, improving yield [5], [6]. We can also cover all path delay faults, some of which may be caused by distributed delay defects, from a few path delay tests [10].…”

Section: Introductionmentioning

confidence: 99%

“…Thus, these methods can be considered equivalent. However, in [5] and [7], the quantized measurement is not considered in the derivation and in [6], the equality constraints are modified to the inequality constraints for the quantized measurement without theoretic justification.…”

Section: Introductionmentioning

confidence: 99%

“…However, directly measuring actual segment delays of a chip is not feasible because most internal nodes of the chip are not observable, and intrusive methods are not practical when the number of segments in the chip and its delay impact on functional paths are considered. Thus, many research contributions [5]- [7] have been devoted to obtaining segment delays from path delays, which contain information on the segment delays. This problem is to solve a linear system of equations, but for practical circuits, the system of equations is underdetermined which is usually considered not solvable.…”

Section: Introductionmentioning

confidence: 99%

“…In [5], segment delays are considered parameters of a statistical model, and the most probable parameters are looked based on the path delay observations. This method is actually similar to finding the maximum a posteriori (MAP) estimate when the measurements are assumed to be accurate.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Segment Delay Learning From Quantized Path Delay Measurements

Chung

Kim

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Our understanding on a silicon chip is limited due to low measurement resolution or model-silicon miscorrelation including variations. This paper shows that chips are better understood by combining noisy measurement results and model information through a mathematical algorithm. Our proposed method learns segment delays in logic circuits from quantized path delay measurements using ridge regression. During the learning process, we take advantage of both nominal segment delays and the delay sensitivity with respect to variations. We also interpret the ridge regression in Bayesian context and in doing so, propose an analytic formula to set the regularization parameter of the ridge regression. For the silicon measurement environments where low measurement resolution is the dominant source of measurement noise, this formula allows us to predict post-silicon results more accurately and speed up the algorithm eliminating inefficient and inaccurate cross-validation. We also demonstrate our method in enhancing the resolution of already measured path delays. We learn segment delays from quantized path delay measurements and predict the path delays prior to the quantization. Our simulation results show that the predicted path delays are much closer to actual values than the measured values and the nominal values.Index Terms-Defect diagnosis, machine learning, post-silicon debug, post-silicon validation.

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Sub-path delay estimation for reconvergent path

Nagatsuka

Takashima

2012

2012 IEEE Asia Pacific Conference on Circuits and Systems

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A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities

Cited by 14 publications

References 26 publications

Delay analysis of sub-path on fabricated chips by several path-delay tests

Delay analysis of sub-path on fabricated chips by several path-delay tests

Segment Delay Learning From Quantized Path Delay Measurements

Sub-path delay estimation for reconvergent path

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