A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits

Neophytou, Stelios; Christou, Kyriakos; Michael, Maria K.

doi:10.1007/s10836-012-5333-0

Cited by 2 publications

(2 citation statements)

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“…This approach is suitable for the PDF test grading problem and it constructs ZDDs with smaller size that those in [36]. However, since the entire paths are not kept in the structure, its applicability to other problems such that of [33] is not guaranteed. In Section 4 we consider both mappings (i.e, [36] and [25]) for rep- resenting all structural paths and for PDF grading.…”

Section: Zdd-based Path Representationmentioning

confidence: 99%

“…In traditional VLSI design, DAGs have been extensively used for representing circuit netlists and physical design layouts In the area of Electronic Design Automation (EDA) the usage of DAGs has been extended to include logic synthesis, module dependencies identification, timing analysis, design verification, postmanufacturing testing, among others [46]. Many of the proposed methodologies targeting these problems involve the graph's paths and corresponding operations on them such as path matching [1,29], identifying paths with specific size [3,38], identifying path overlap [33], union and intersection on path sets [7], etc.…”

Section: Introductionmentioning

confidence: 99%

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Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering

Neophytou

Michael

2018

J Electron Test

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The efficient representation and manipulation of a large number of paths in a Directed Acyclic Graph (DAG) requires the usage of special data structures that may become of exponential size with respect to the size of the graph. Several methodologies targeting Electronic Design Automation problems such as timing analysis, physical design, verification and testing involve path representation and necessary manipulation. Previous works proposed an encoding using Zerosuppressed Binary Decision Diagrams (ZDDs), which has been shown experimentally to cope well when representing structural or logical paths in VLSI circuits. However, it is well known that the ordering of the variables in a ZDD highly affects its size and, therefore, the efficiency of the methodologies utilizing these data structures. In this work, we show that using a reverse topological order for the ZDD variables bounds the number of nodes in the ZDD representing structural paths to the number of edges in the DAG considered, hence, making the ZDD size linear to the DAG's size. This result, supported here both theoretically and experimentally, is very important as it can render methodologies with questionable scalability applicable to larger industrial designs. We demonstrate the applicability of

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