A noise cancellation technique in active RF-CMOS mixers

This article presents the analysis, design, and implementation of a 60 GHz transmitter in 130 nm bulk CMOS, focusing on low power and high performance applications. The low power transmitter lineup consists of two double‐balanced Gilbert‐cells with dynamic current injection, on chip FGCPW meandering ring‐hybrid balun, Lange coupler, combiner, preamplifier, and low power transformer coupled power amplifier. A planar antenna with above 6 dB gain is also implemented. The measured output −1 dB compression point of the power amplifier is 9.6 dBm with 8.6 dB gain, and the 3 dB bandwidth is from 47 to 67 GHz (power amplifier) while drawing 90 mA from a 1.2 V supply. The mixer, preamplifer, and drive amplifier consume 12, 26, and 68 mA, respectively. The transmitter up‐converting an IF of 200 MHz to RF at 60.2 GHz achieve a total gain of 17.17 dB (simulated 21.09 dB) and saturation power higher than 9.53 dBm. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:785–789, 2015

Section: Received 28 August 2014mentioning

confidence: 99%

A 60 GHz low power direct‐conversion quadrature‐phase transmitter in 130 nm CMOS with low profile cavity backed antenna

Chen

Shen

et al. 2015

“…Figure 1 shows the schematic diagram of the proposed mixer. In order to reduce direct and indirect flicker noise generation a dynamic current injection technique [6] using three p-type MOS (PMOS) switches has been used. These PMOS switches, M1-M3, inject current impulses equal to the bias current of each pair of switches to cancel the noise pulses generated at the output at only the switching instances.…”

Section: Flicker Noise Mechanisms In Gilbert-cell Mixermentioning

confidence: 99%

“…Many designs have been proposed to reduce the output flicker noise of the mixer. Static current injection has been proposed in [5], dynamic current injection proposed in [6], and the same design in [6] has been used by Yoon et al [7], with a shunt tuning inductor has been added to reduce the effect of tail capacitance (Cp) at the node between the local oscillator (LO) switches and RF transconductance stage. This design in [7] gives a good results but it sacrifices the chip size by using a bulky spiral inductor.…”

Section: Introductionmentioning

confidence: 99%

Flicker noise reduction in RF CMOS mixer using differential active inductor

Abdelghany

Pokharel

Kanaya

et al. 2011

This article presents a low flicker noise (1/f), doublebalanced Gilbert-cell mixer. As the down converted base-band signal is strongly affected by the low-frequency flicker noise, resulting in mixer signal-noise ratio (SNR) degradation, a dynamic current injection technique has been used to reduce the flicker noise corner frequency. Differential active inductor has been used to tune the tail capacitance at the node between the local oscillator (LO) switches and the radio frequency (RF) transconductance stages, resulting in reduction of RF leakage. RF and LO leakage has been minimized by adding an on-chip low-pass filter to the mixer output. The mixer has been designed and fabricated using Taiwan Semiconductor Manufacture Company (TSMC) 0.18-lm 1P6M complementary metal-oxide-semiconductor FET (CMOS) process. The performance of the fully integrated mixer is given. With RF of 2.4 GHz, intermediate frequency of 10 MHz and LO power of À5 dBm, conversion gain of 12 dB, input third order intercept point (IIP3) of À5.5 dBm, and single-side band noise (SSB-NF) figure of 15 dB with flicker noise corner frequency of 300 KHz had been measured. The mixer consumes 19.8 mW from 1.8 V supply.

“…To reduce the consumed dc power, the bulk‐driven method is proposed with cost of increasing the local oscillator (LO) pumping power. Furthermore, there are other techniques on noise and intermodulation performance improvements to enhance the mixer receiving dynamic range.…”

Section: Introductionmentioning

confidence: 99%

Design of resistive double‐balanced mixer in 0.18‐μm CMOS technology with low‐power bulk‐injection technique for 5.8‐GHz DSRC applications

Huang

Guu

Chen

et al. 2014

This article shows a 0.18‐µm CMOS resistive double‐balanced mixer design with low‐noise figure and high‐linearity performances, consuming only 0.21‐mW dc power, for 5.8‐GHz dedicated short‐range communications (DSRC) applications. The local oscillator (LO) signal is applied to the bulk and the source terminals differentially to reduce the required LO power without needs of impedance matching. The on‐chip central‐taped transformers are utilized as balance‐to‐unbalance function for RF and LO ports, and the differential output is used as well for intermediate‐frequency (IF) port. The measured data exhibit −8‐dB conversion gain and 8‐dB noise figure at 5.8 GHz of RF frequency and 100 MHz of IF frequency, while the input 1‐dB compression point and the input interception point in the third order (IP3) are about −7.5 and 3 dBm, respectively, to fulfill the DSRC requirements. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1248–1251, 2014