A NoC system generator for the Sea-of-Cores era

Öberg, Johnny; Robino, Francesco

doi:10.1145/2157871.2157875

Cited by 10 publications

(6 citation statements)

References 10 publications

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“…To evaluate its performance, the proposed wireless communication is simulated in Ansys High Frequency Structured Simulator (HFSS) [16,17]. Here, we investigated on a wide range of WiNoC configurations.…”

Section: Experimental Results and Set-upmentioning

confidence: 99%

Congestion-aware wireless network-on-chip for high-speed communication

2019

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The design of system-on-chip (SoC) requires the complex integration between a multi-number of cores on a single chip. To establish the effective communication between multiple cores there aremore challenging issues on designing the network-on-chip (NoC) architectures. The proposed system deals with the utilization of on-chip antennas for the wireless communication between the long distance cores to minimize the latency and power. In this proposed work, we have designed high-speed wireless NoC (WiNoC) for on-chip communication. This high-speed WiNoC has been achieved by designing a congestion measure unit, which monitors and measures the congestion in the input data and establishes the effective wireless communication between the output channels and routers. The designed architecture is synthesized and implemented by using Altera Quartus II, where the SoC is designed using Qsys builder. The proposed WiNoC shows better performance parameters like throughput, latency and power than the conventional NoC.

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Section: Experimental Results and Set-upmentioning

confidence: 99%

Congestion-aware wireless network-on-chip for high-speed communication

2019

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“…Although the framework enables a vast and extensive exploration of NoC topologies, it only uses one hard coded processing core, thus limiting the possibility to explore the heterogeneity at the core level. Similarly,Öberg et al [16] have proposed a NoC exploration platform, which can generate 1D, 2D or 3D Mesh and Torus topologies for multicore platforms. Their NoC generator generates an arbitrarily large multicore platform through an XML configuration file.…”

Section: Related Workmentioning

confidence: 99%

Towards Architectural Design Space Exploration for Heterogeneous Manycores

Xypolitidis

Shabani

Khandeparkar

et al. 2016

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

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Abstract-Today many of the high performance embedded processors already contain multiple processor cores and we see heterogeneous manycore architectures being proposed. Therefore it is very desirable to have a fast way to explore various heterogeneous architectures through the use of an architectural design space exploration tool, giving the designer the option to explore design alternatives before the physical implementation.In this paper, we have extended Heracles, a design space exploration tool for (homogeneous) manycore architectures, to incorporate different types of processing cores, and thus allow us to model heterogeneity. Our tool, called the Heterogeneous Heracles System (HHS), can besides the already supported MIPS core also include OpenRISC cores. The new tool retains the possibility available in Heracles to perform register transfer level (RTL) simulations of each explored architecture in Verilog as well as synthesizing it to field-programmable gate arrays (FPGAs). To facilitate the exploration of heterogeneous architectures, we have also extended the graphical user interface (GUI) to support heterogeneity. This GUI provides options to configure the types of core, core settings, memory system and network topology.Some initial results on FPGA utilization are presented from synthesizing both homogeneous and heterogeneous manycore architectures, as well as some benchmark results from both simulated and synthesized architectures.

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“…The scalable multi-core NOC platform is generated from an XML configuration file [27]. The basic configuration includes target technology, NOC topology, kind of router and interconnection scheme.…”

Section: Noc Generatormentioning

confidence: 99%

Going for Brain-Scale Integration - using FPGAs, TSVs and NOC based Artificial Neural Networks

Mand

Öberg

2014

Proceedings of the FPGA World Conference 2014

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With better understanding of brain's massive parallel processing, brain-scale integration has been announced as one of the key research area in modern times and numerous efforts has been done to mimic such models. Multicore architectures, Network-OnChip, 3D stacked ICs with TSVs, FPGA's growth beyond Moore's law and new design methodologies like high level synthesis will ultimately lead us toward single-and multi-chip solutions of Artificial Neural Net models comprising of millions or even more neurons per chip. Historically ANNs have been emulated as either software models, ASICs or a hybrid of both. Software models are very slow while ASICs based designs lacks plasticity. FPGA consumes a little more power but offer the flexibility of software and performance of ASICs along with basic requirement of plasticity in the form of reconfigurability. However, the traditional bottom up approach for building large ANN models is no more feasible and wiring along with memory becomes major bottlenecks when considering networks comprised of large number of neurons. The aim of this paper is to present a design space exploration of large-scale ANN models using a scalable NOC based architecture together with high level synthesis tools to explore the feasibility of implementing brain-scale ANNs on FPGAs using 3D stacked memory structures. .

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A NoC system generator for the Sea-of-Cores era

Cited by 10 publications

References 10 publications

Congestion-aware wireless network-on-chip for high-speed communication

Congestion-aware wireless network-on-chip for high-speed communication

Towards Architectural Design Space Exploration for Heterogeneous Manycores

Going for Brain-Scale Integration - using FPGAs, TSVs and NOC based Artificial Neural Networks

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