A new write assist technique for SRAM design in 65 nm CMOS technology

Farkhani, Hooman; Peiravi, Ali; Moradi, Farshad

doi:10.1016/j.vlsi.2015.01.001

Cited by 10 publications

(13 citation statements)

References 27 publications

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“…Application of a negative voltage −∆V instead of ground leads strengthening of the access device connected to cell node storing a high voltage and considerable improvement of write-ability of the cell [19][20][21][22][23][24][25] . Negative bit-line voltage has been produced by the use of C Boost instead of a separate negative voltage generator charge pump circuit.…”

Section: Negative Bit-line Assist Techniquementioning

confidence: 99%

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A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology

et al. 2018

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A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line (BNBL) provides 47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line (NBL) and boosted bit line (BBL) write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology.

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Section: Negative Bit-line Assist Techniquementioning

confidence: 99%

“…Design proposed in Ref. [18] uses replica bit-line and replica buffer to determine the time when C boost should be connected to bit-line. REBL together with the delay block is used to determine the time when boosting capacitor should be connected to the bit-line.…”

Section: Negative Bit-line Assist Techniquementioning

confidence: 99%

A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology

et al. 2018

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“…Although supply voltage scaling has been proved to be the most effective method for energy saving [1,2,3,4,5,6], it will seriously deteriorate the read stability and write ability of the memory cell. Moreover, due to the process variations existing, the performance described above will be further deteriorated in low voltage, also in the future process nodes, which will result in the failure probability of read or write operations increasing [2,6,7,8,9,10]. Thus, the trade-off between performance and power should be considered.…”

Section: Introductionmentioning

confidence: 99%

“…To improve the write margin and read stability for conventional 6T SRAM, different types SRAM cell topologies as well as assist circuit has been proposed [1,2,3,6,7,8,9,10,11,12,13]. Decoupling the storage nodes with bit-line or lowering the voltage drop between the driver and access transistors is the efficient way to enhance read stability [11].…”

Section: Introductionmentioning

confidence: 99%

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Read/write margin enhanced 10T SRAM for low voltage application

Peng

Guan

et al. 2016

IEICE Electron. Express

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Abstract:The static random access memory (SRAM) is indispensable for high performance applications. With technology scaling, the device size as well as the operation supply voltage (VDD) is reduced. However, with the supply voltage decreasing, the performance of the conventional 6T SRAM is deteriorated seriously. In this letter, a symmetrical 10T SRAM with dramatically improved read stability and write ability is proposed. The simulation results indicate that, compared with the conventional 6T SRAM, the read static noise margin (RSNM) and write margin (WM) of the proposed 10T SRAM achieve 2.43× and 4.51× improvement, respectively, at a 0.8 V supply voltage in SMIC 65 nm technology. As a result, lower failure probability in access operations is expected. Moreover, the minimum supply voltage (VDD min ) of the proposed 10T SRAM achieves ∼0.32× compared with that of conventional 6T cell. Additionally, it also shows a better tolerance to the varying process variations.

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Cost-Effective Computational Modeling of Fault Tolerant Optimization of FinFET-Based SRAM Cells

Girish

Shashikumar

2017

Advances in Intelligent Systems and Computing

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A new write assist technique for SRAM design in 65 nm CMOS technology

Cited by 10 publications

References 27 publications

A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology

A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology

Read/write margin enhanced 10T SRAM for low voltage application

Cost-Effective Computational Modeling of Fault Tolerant Optimization of FinFET-Based SRAM Cells

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