A new watermarking method for soft IP protection

Yu, Tingting; Zhu, Yuesheng

doi:10.1109/cecnet.2011.5768190

Cited by 10 publications

(2 citation statements)

References 4 publications

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“…This strategy allows easy application but provides low security levels, since the independent module containing the information identifying the IP core could be removed without affecting the correct functioning of the original IP core. This drawback was addressed by Yu and Zhu [ 25 ], but neither automation nor computation times are shown for the proposed method. Other strategy is based on changes into the original structure of the design [ 19 , 26 ].…”

Section: Methodsmentioning

confidence: 97%

Design Time Optimization for Hardware Watermarking Protection of HDL Designs

Castillo

Morales

García

et al. 2015

The Scientific World Journal

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HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original system. The development of this new tool for the signature distribution has not only extended and eased the applicability of this IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties on the IP core to protect. An 1D-DWT core and MD5 and SHA1 digital signatures were used in order to illustrate the benefits of the new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer effort and time.

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Section: Methodsmentioning

confidence: 97%

Design Time Optimization for Hardware Watermarking Protection of HDL Designs

Castillo

Morales

García

et al. 2015

The Scientific World Journal

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“…Our method can be easily adopted by current and future set of design tools, which use either hardware description language (HDL) or high level language for IP generation. In other words, the proposed watermarking methodology applies to the protection of both hardware and software IP [19]. Our method not only allows the designer to embed a robust multi-variable signature into the design but enables exploration of an optimal watermarked solution.…”

Section: Introductionmentioning

confidence: 98%

Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis

Sengupta

Bhadauria

2016

IEEE Access

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The challenges in the current design process for consumer electronics products include greater complexity and stiff time-to-market pressure, which has led to the usage of reusable intellectual property (IP) cores (such as JPEG and MPEG) as a sustainable solution. This has led to the domain of IP protection for anti-piracy as an important subject of research for a system design. Watermarking is expected to provide the best protection of authorship when applied at higher levels, i.e., during high-level synthesis. It is also well acknowledged that watermark insertion is non-trivial, as it is very difficult to choose a strong signature that results in higher security and less area overhead among available design solutions. This paper presents a novel multi-variable signature encoding for embedding a dynamic watermark in an IP design during architectural synthesis that provides enhanced security against typical attacks. Owing to the involvement of multiple (four) variables in the proposed signature, it is difficult to realize the signature without complete encoding knowledge of the four variables. Second, our approach aims to optimize the embedding cost of the watermark by exploring a low-cost solution through particle swarm optimization-driven design space exploration based on area-delay constraints. Comparison with a recent technique indicated that our watermark incurs lower embedding cost, lower runtime, and less storage hardware.INDEX TERMS IP security, watermark, design abstraction, high level synthesis, design space exploration, particle swarm optimization, optimization, area-delay constraints.

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Low Cost Dual-Phase Watermark for Protecting CE Devices in IoT Framework

Sengupta

Roy

2018

Internet of Things

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A new watermarking method for soft IP protection

Cited by 10 publications

References 4 publications

Design Time Optimization for Hardware Watermarking Protection of HDL Designs

Design Time Optimization for Hardware Watermarking Protection of HDL Designs

Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis

Low Cost Dual-Phase Watermark for Protecting CE Devices in IoT Framework

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