A new VLSI architecture suitable for multidimensional order statistic filtering

IEEE Trans. Circuits Syst. Video Technol.

Kuo

1998

Based on the recently developed sorting networks, a new VLSI architecture suitable for two-dimensional (2-D) rankorder filtering is proposed. The major advantage of the proposed architecture is their fast response time, modular architecture, and simple and regular interconnection. Generally speaking, the throughput of the proposed architecture is (N 0 1) times faster than using a one-dimensional rank-order filter for 2-D N 2 N data. The concept of block processing is also incorporated into the design to reduce the time-area complexity of the proposed architecture. Roughly speaking, the complexity is reduced to 2/3 and 1/2 compared with a rank-order and median filter without using block processing architecture, respectively. A 3 2 3 median filter with block processing architecture is implemented through a 0.8 m single-poly double-metal CMOS process. The results are correct with a clock rate up to 125 MHz.Index Terms-Block processing, max-min sorting network, rank-order filter.

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Two-dimensional rank-order filter by using max-min sorting network

IEEE Trans. Circuits Syst. Video Technol.

Kuo

1998

“…Many approaches for hardware implementation of rank-order filtering have been presented in the past decades [8,[10][11][12][13][14][15][16][17][18][19][20][21][22][23][24]. Many of them are based on sorting algorithm [11,22,23,[25][26][27][28].…”

Section: Introductionmentioning

confidence: 99%

“…These architectures are fully pipelined for high throughput rate at the expense of latency, but require a large number of compare-swap units and registers. To reduce the hardware complexity, papers [8,12,14,15,[29][30][31][32] present lineararray structures to maintain samples in sorted order. For a sliding window of size N, the lineararray architectures consist of N processing elements and require three steps for each iteration: finding the proper location for new coming sample, discarding the eldest one, and moving samples between the newest and eldest one position.…”

Section: Introductionmentioning

confidence: 99%

On VLSI design of rank-order filtering using DCRAM architecture

Dung

2008

Integration

This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for realtime speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm 2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

Fast response 2-D rank order filter by using max-min sorting network

Proceedings of 3rd IEEE International Conference on Image Processing

Kuo²

Based on the recently developed sorting networks, a new VLSI architecture suitable for 2-D rank order filtering is proposed. The major advantage of the proposed architecture is their fast response time and modular architecture. Generally speaking, the throughput of the proposed architecture is (N-1) times faster than using a 1-D rank order filter for 2D N x N data.The concept of block processing is also incorporated into the design to reduce the time-area complexity of the proposed architecture. Roughly speaking, the complexity is reduced to 2/3 and 1/2 compared with a rank order and median filter without using block processing architecture, respectively. A 3 x 3 median filter with block processing architecture is implemented through a 0.8,um single-poly double metal CMOS process. The simulation results are correct with a clock rate up to 91MHz.