A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor

Abstract

The demand for high resolution CMOS image sensors (CIS) is rising. Analog-to-digital converters (ADC) represent one of the major bottleneck of CIS. One of the candidates to overcome the existing limits is the column-parallel ADC. Column-parallel extended counting ADCs (EC-ADC) are able to reach high resolution thanks to their two-step conversion. However the EC-ADC area increases due to the two-step design. A solution is to use the same hardware twice to perform both steps. This paper proposes a 14-b, 100 kHz Nyquist frequency, two-step incremental Σ∆ (IΣ∆) analogto-digital converter suitable for column-parallel CIS. Several architectures with different modulator order are compared to determine the most promising one. The proposed architecture, compared to a one-step second order modulator, reduces the total oversampling ratio (OSR) from 150 to 60 to reach a resolution of 14-b. The operational transconductance amplifiers (OTA) is the most critical part in our ADCs. Its required DCgain is around 80 dB for a 120 MHz gain-bandwidth product (GBW). The ideal DNL and INL of our two-step IΣ∆ ADC are respectively +0.55/-0.6 LSB and +0.5/-0.5 LSB. This work achieves a SNDR of 89 dB when a full scale sinusoid of 100 kHz is applied.

A 14-bit 250 kS/s two-step inverter-based incremental $$\varSigma \varDelta$$ Σ Δ ADC for CMOS image sensor in $$0.18\,\upmu \hbox {m}$$

“…where i=1,2, M 2 is the number of samples for the second step, S 2 the bitstream of the fine conversion and K i the coefficient associated with the coarse and fine conversion. To maximize the resolution, M 1 and M 2 must be equal [1]. We take M 1 = M 2 = 35 to reach the aimed resolution.…”

“…The second case is investigated in this section. The output linearity swing is the output range of the amplifier where a minimum DC gain of 80 dB is ensured [1]. A monte-carlo analysis of the inverter is realized and the output linearity is observed.…”

A 14-b two-step inverter-based ΣΔ ADC for CMOS image sensor

“…where M 2 is the number of samples for the second step, S 2 the bitstream of the fine conversion and K i the coefficient associated with the coarse and fine conversion. To maximize the resolution, M 1 and M 2 must be equal [9] with M 1 = M 2 = 35. In a two-step ADC the range difference between the output of the first step of the conversion (V 2 [M 1 ]) and the effective input of the second step can highly deteriorate the overall resolution.…”

“…To perform a 14-bit resolution conversion, a minimum DC gain of 76 dB is needed [9]. The DC gain of an inverter is expressed as follows…”

“…Thanks to the gain boosting amplifier circuit, the effective transconductance of the cascode transistor is increased, hence considerably increasing the output resistance of the inverter-based amplifier. The output linearity swing is the output range of the amplifier where a minimum DC gain of 76 dB is ensured [9]. A trade-off has to be found between the maximum DC gain and output linearity.…”