A new test scheduling algorithm for VLSI systems

Abstract

This paper presents a new test scheduling algorithm based on a new heuristic approach. A new concept of Time Zone Tree has been proposed and the algorithm builds up the tree based on a heuristic cost function. The performance of the algorithm has been compared with the existing algorithms and at demonstrates encouraging results.

Introduction to Advanced System-on-Chip Test Design and Optimization

“…This type of conflicts can be modeled using a resource graph as used by Garg et al (Figure 68) [65]. It can be conflicts such that a part of the system has to be used while another part is tested.…”

“…However, a core can also be embedded in a core. This is a type of conflict that is known in advance and hence it can be modeled using a test resource graph as proposed by Garg et al [65] and by Larsson et al [176,166] (Section 3.1). The embedding of cores in cores results in conflicts at testing.…”

An Integrated Framework for the Design and Optimization of SOC Test Solutions

“…For instance, the approach by Garg et al [11] and by Chakrabarty [5] both has a worst case complexity of O(n 3 ).…”

“…Several heuristics have been proposed [1,4,5,9,11,14,23,27]; however, they have been evaluated using rather small benchmarks. For such benchmarks, a technique based on Mixed-Integer Linear-Programming (MILP) can be used [4].…”

Hybrid BIST time minimization for core-based systems with STUMPS architecture

“…Some approaches can also take into account test conflicts and different constraints, e.g. power [4] - [11]. Sugihara et al [8] have addressed the problem of selecting a test set for each core from a set of pre-determined test sets provided by the core vendor and scheduling these tests in order to minimize the testing time.…”