A new technique for background calibration of pipelined ADCs

Abstract

This paper presents a new background calibration technique for pipelined ADCs by means of slow high accurate ADC (SHADC). Errors due to finite and nonlinear gain of inter-stage operational amplifier are calibrated. Correction coefficients are estimated by using the well-known LMS algorithm. Obtained results from simulation of a 13bit 1.5bit/stage pipelined ADC behavioral model reveals the effectiveness of the proposed technique to calibrate the mentioned errors. The ADC achieves a DNL of -0.8 LSB from -47.03 LSB, an INL of 2.84 LSB from 66.48 LSB and SNDR of 73.55 dB from 40.64 dB after calibration.