A New SRAM-Embedded Pixel Circuit That Modulates Accurately Gray Level for PWM-Driven Micro-LED Displays

A High 5292-PPI Pixel Circuit for Micro Displays With 10-Bit Gray Levels Realized via the Technique of Analog Sub-Frame Integral

“…Based on the PWM, the technique of pulse density modulation (PDM) was developed to run dimming the discontinuity of luminance intensity between frames for improving false contour without a speedy refresh rate [14]- [16], but this optical artifact is not perfectly eliminated on such digitally driven schemes of impulse illuminating. The technique of analog PWM (A-PWM), a PWM-behaved scheme that outputs its I pixel by hold type illuminating and functions by inputting analog data voltages (V data 's) into the pixel circuit to modulate illuminating time [17]- [19], could rule out false contours completely since the variations of the illuminating time between adjacent gray levels are continuously consistent, performed the same effectiveness to the other hold illuminating schemes of pulse amplitude modulation (PAM) that runs with V data 's to obtain different I pixel 's in a fixed illuminating time [20]- [22]. However, the pixels of these hold-illuminating type driving are commonly built with the circuits that are of complicated structure for running with the minimum voltage of 5.12V to realize 1024 (10-bit) gray levels when the one least significant bit (1-LSB) of the analog voltage is assumed 5mV, where the necessary of at least 5.12V-driven high voltage FETs (HVFETs) are required to construct these pixel circuits.…”

“…2 shows the four phases of the proposed circuit running with its corresponding timing depicting in Fig. 3, the first two are for generating initial current of I pixel (I P-I ) at the 1st Possible FET Configuration to build the 10-bit Pixel Circuit [7] 2 HV-and 1 LV-FETs [8] 1 HV-and 1 LV-FETs [9] 1 HV-and 1 LV-FETs [14] 1 HV-and 1 LV-FETs [15] 1 HV-and 1 LV-FETs [16] 1 HV-and 1 LV-FETs [17] sub-frame and the last two happened at the 2nd or beyond sub-frame would switch the output current to an updated I pixel (I P-U ), where the number of sub-frames is 8 (3-bit). In phase-1, V data1 and V data2 are respectively delivered to the nodes of na and nc, the logic 1 of V sel biases node ne, node nd receives logic 0 via INV1; then these logics would be maintained with the latch made of INV1 and INV2, making T4 turned on and delivering V ref to node nb.…”