A New Spatiotemporal CMOS Imager With Analog Accumulation Capability for Nanosecond Low-Power Pulse Detections

Ultrafast Imaging in Standard (Bi)CMOS Technology

“…The detailed block diagram of a second generation pixel array-based sensor is shown in Fig. 7 (Morel et al 2006). The circuit features an array of n × m active pixels, an m-stage temporal axis generator for the sweep unit, and two selection circuits and an output amplifier for serial data read-out.…”

“…The 6T active pixel is also featuring an analog accumulation capability (Morel et al 2006). Before acquisition, the potential on the cathode of the photodiode is initialized to V RPD and the potential on the read-out node RN to VRR.…”

12 × 7.14 GS/s rate time-resolved BiCMOS imager

“…M 3 is used to initialize the potential on node A before data acquisition. During data read-out, M 4 Figure 3. Schematic diagram of a single circuit row with detailed sampling cell architecture.…”

“…Typical applications in which a 100 psorder temporal resolution is required are bacteria identification by fluorescence [1], laser-Doppler velocimetry [2], or the study of random transitional phenomena in Micro-Electro-Mechanical Systems (MEMS) [3]. Work on time-resolved high-speed CMOS imagers has already been reported [4], [5]. In [4], a time-resolved CMOS imager with an on-chip analog accumulation capability is presented.…”

“…Work on time-resolved high-speed CMOS imagers has already been reported [4], [5]. In [4], a time-resolved CMOS imager with an on-chip analog accumulation capability is presented. It is based on a 64 × 64 pixel array and features a fixed 1.56 GS/s sampling rate.…”