A new self-align technology for GaAs analog MMIC's

Formation of a submicron GaAs MESFET gate using a four-layer dielectric dummy gate

“…1) has the following advan tages over less complicated shapes of one , two , or three layer dielectric dummy gates [13][14][15][16][17]: first, the wide base of the lower layer 1 provides the mechanical strength of the dummy gate and its adhesion to the substrate. Second, a combination of wide (2) and nar row (3) parts of the dummy gate, involving the second and the third dielectric layers, makes the profile nega tive, which is essential to obtaining a high quality sub micron metal gate electrode by lift off lithography, with a narrow part 3 determining the gate length.…”

“…One of the cutting edge tech niques enabling one to obtain MESFETs with high per formance is the technique of self aligned device ele ments, particularly, self aligned gate and source and drain contact regions of the transistor [5][6][7][8][9][10][11][12][13][14][15][16][17]. The dis tinctive features of this method are the fact that the res olution of the lithography under use is much higher than the obtained gate length, and that the constitutive operations are performed in the following sequence: Formation of a large sized self aligned element.…”

“…In the first one, a gate based on refractory metallization acts as a self alignment element, which can withstand activation high temperature annealing of an ion implanted layer (IIL) at T ≥ 850°С [5][6][7][8][9]. In the second group, a one , two , or three layer dielectric dummy gate is used as a self aligned element, which, on IIL high temperature annealing and diminishing dummy date length, is replaced by a metal gate [9][10][11][12][13][14][15][16][17]. The drawback of the first type of technologies is the significant resistivity of the refractory gate metallization, leading to the degra dation of MESFET frequency characteristics.…”

Optimization of the self-aligned GaAs MESFET with the multilayer dielectric “dummy gate“ for a high power microwave applications

“…The several technological approaches for the self-aligned gate MESFETs production are reported in the literature [1][2][3][4][5], the majority of which can be divided on two groups of the base processes: "low temperature", and "high temperature" metal gates. The high temperature process utilizes the refractory metal or alloy (WSi, WSiN, TiWN and etc) to define the gate geometry before the n + implantation [1,2].…”

“…The high temperature process utilizes the refractory metal or alloy (WSi, WSiN, TiWN and etc) to define the gate geometry before the n + implantation [1,2]. The low temperature approach utilizes the single or double-layer dielectric "dummy gate" to mask the n + implantation, replaced by the gate metal only after the high temperature annealing by means of a complex resist planarization and dielectric etch sequence [3][4][5].…”