A New Real-Time FPGA-Based Implementation of K-Means Clustering for Images

Deng, Tiantai; Crookes, Danny; Siddiqui, Fahad; Woods, Roger

doi:10.1007/978-981-13-2384-3_44

Cited by 2 publications

(1 citation statement)

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“…There are several previous works that propose FPGA-based implementations of k-means, but none of them are purely RTL hardware designs built from the ground up. Instead, they use techniques like HLS [39], [40], which partially automates the hardware implementation process, simplifying development at a cost of reducing scalability (since both references are unable to change the number of clusters) and sacrificing performance due to tool limitations. There are also hardware-software codesigns [24], that despite of their flexibility, fail to accelerate the whole algorithm and still conceive k-means as a sequence of instructions, causing a bottleneck.…”

Section: Comparison To Previous Workmentioning

confidence: 99%

Parametric Pipelined k-Means Implementation for Hyperspectral Processing on Spacecraft Embedded FPGA

Morcillo,

Báscones,

González

et al. 2024

IEEE J. Sel. Top. Appl. Earth Observations Remote Sensing

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k-means stands out as one of the most common clustering algorithms, widely employed for classification in hyperspectral imaging. In this context, large amounts of data are gathered by sensors that are embedded into satellites with strict constraints in terms of power consumption, weight, physical space or radiation tolerance. Since communication bandwidth is also limited, data processing must be performed on board. However, meeting all those constraints also entails a significant trade-off with computing performance. The aim of this work is clustering hyperspectral images in real-time. Custom hardware has been designed with the objective of reducing overhead and maximizing performance, by exploiting several acceleration techniques. The implementation targets a space-grade Xilinx Kintex FPGA, that features low power consumption and is shielded against radiation. The design has a deep pipelined architecture, able to process all bands of each hyperspectral pixel in parallel. In consequence, it attains a throughput of 100M hyperspectral pixels per second, even with a discrete use of FPGA resources. In addition, it is also fully parametric, with on-the-fly adaptation to different kinds of images and clustering configurations.Compared to previous implementations, ours takes advantage of a fully RTL design that avoids CPU bottlenecks and HLS design overheads. It also has a fixed throughput regardless of image or clustering properties, while having lower FPGA resource usage than performance-wise equivalent implementations.

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Section: Comparison To Previous Workmentioning

confidence: 99%