A New Quaternary Full Adder Cell based on CNFET for Use in Fast Arithmetic Circuits

Abstract

Multi-valued logic potentially increases the efficiency of arithmetic circuits and digital ‎signal processing. Quaternary logic can be suggested as a solution to the problem of power ‎consumption and connection complexity in binary digital systems. The possibility of having ‎several threshold voltage levels using the carbon nanotube field-effect transistor ‎results in the widespread use of this technology in the design of multi-valued circuits. Here, a quaternary full adder cell is proposed. The main goal of the proposed circuit ‎is to reduce the critical delay path in the quaternary full adder circuit using a parallel ‎design. The proposed circuit is compared with four quaternary full adders based on ‎simulation results using HSPICE in 32 nm technology. The experimental results show the ‎higher performance of the proposed quaternary full adder cell than the state-of-the-art ‎designs.‎