A new prediction method for oxide lifetime and its application to study dielectric breakdown mechanism

Okada, Kenji; Kubo, Hiroko; Ishinaga, A.; Yoneda, Kenji

doi:10.1109/vlsit.1998.689239

Cited by 33 publications

(13 citation statements)

References 5 publications

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“…This has been the assumption whenever measurements at elevated voltage have been used to project oxide reliability down to operating conditions [104], [109]- [113]. Several experiments have supported this assumption, using various measurements of the defect density including interface states, trapped charge, and stress-induced leakage.…”

Section: The Critical Defect Densitymentioning

confidence: 97%

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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Abstract-The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 nm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO 2 -based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1% of these paths ultimately lead to destructive breakdown, and the microscopic nature of these defects is not known. The rate of defect generation decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron-induced hydrogen release. However, the tunnel current also increases exponentially with decreasing oxide thickness, leading to a decreasing time-to-breakdown and a diminishing margin for reliability as device dimensions are scaled. Estimating the reliability of the dielectric requires an extrapolation from the measurement conditions (e.g., higher voltage) to operation conditions. Because of the diminished reliability margin, it has become imperative to try to reduce the error in this extrapolation.Long-term ( 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin ( 2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown. Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

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Section: The Critical Defect Densitymentioning

confidence: 97%

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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“…Consequently, SILC, either bulk trap or interface trap related, has been used as a degradation monitor and time-to-breakdown predictor. 54,60,347,[389][390][391]…”

Section: Stress-induced Leakage Currentmentioning

confidence: 99%

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Green¹,

Gusev

Degraeve

et al. 2001

Journal of Applied Physics

746

345

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The outstanding properties of SiO 2 , which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO 2 interface, which forms the heart of the modern metal-oxide-semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin ͑Ͻ4 nm͒ SiO 2 and Si-ON ͑silicon oxynitride͒ gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices will be manufactured with SiO 2 and Si-ON for the foreseeable future, continued scaling of integrated circuit devices, essentially the continued adherence to Moore's law, will necessitate the introduction of an alternate gate dielectric once the SiO 2 gate dielectric thickness approaches ϳ1.2 nm. It is hoped that this article will prove useful to members of the silicon microelectronics community, newcomers to the gate dielectrics field, practitioners in allied fields, and graduate students. Parts of this article have been adapted from earlier articles by the authors ͓L.

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“…This power law dependence was observed for short stress time, but for longer stress periods, saturation was observed for all stress voltages. It was earlier reported that SILC has a power-law dependence on stress time (8), and the exponent of the power-law was reported to be 0.5 (9), which led to the explanation that trap generation is related to a (hydrogen) diffusion process through the oxide. For the gate stack considered here, the power-law exponent of 0.66 indicates different precursor defects which are oxygen vacancies.…”

Section: Resultsmentioning

confidence: 99%

Low Voltage SILC Analysis for High-k/metal Gate Dielectrics

Rahim

Misra²

2009

ECS Trans.

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Conduction behavior of multi-layer structure of metal/high-k/interfacial layer gate stacks was investigated before and after constant voltage stress. It was found that stress-induced leakage current (SILC) strongly depends on the low sense voltages. Conduction mechanism of the low voltage SILC (LV-SILC) was analyzed systematically with gate stacks of different interfacial layer thicknesses and SiO2-only devices of identical processing condition. Based on the results of defect generation sensed by the LV-SILC, it is observed that discrete levels of trap generation in the interfacial layer primarily causes low voltage SILC in metal/high-k gate stacks and initiates the gate stack breakdown.

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A new prediction method for oxide lifetime and its application to study dielectric breakdown mechanism

Cited by 33 publications

References 5 publications

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Low Voltage SILC Analysis for High-k/metal Gate Dielectrics

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A new prediction method for oxide lifetime and its application to study dielectric breakdown mechanism

Cited by 33 publications

References 5 publications

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Ultrathin (&lt;4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Low Voltage SILC Analysis for High-k/metal Gate Dielectrics

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Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits