A new placement algorithm minimizing path delays

Hasegawa, Takashi

doi:10.1109/iscas.1991.176807

Cited by 9 publications

(2 citation statements)

References 9 publications

(1 reference statement)

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“…There have been many studies about timing-driven placement, and they can be classified into the following four approaches, (1) the net weighting approach [l, 3,15,17,20], (2) the net delay bounds approach [6,9,10, 16,211, (3) the path weighting approach [8,22], and (4) the path delay bounds approach [2,7,11,12,19]. However, many of them have a difficulty of trade-off between the quality of the layout and the computation time.…”

Section: Introductionmentioning

confidence: 99%

Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs

Koide

Ono²,

Wakabayashi³

et al.

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

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In this paper, we present a parallel algorithm running on a shared memory multi-processor workstation for timing driven standard cell layout. The proposed algorithm is based on POPINS2.0 [13] and consists of three phases. First, we get an initial placement by a hierarchical timing-driven mincut placement algorithm. At the top level of partitioning hierarchy, we perform one step of bi-partitioning by several processors, and in the lower levels of partitioning hierarchy, partitionings of each region in a level are performed in parallel. Next, in phase 2, iterative improvement of the sub-circuit which contains critical paths is performed by nonlinear programming. Parallel processing is realized by performing the nonlinear programming method to each sub-circuit in parallel. Finally, in phase 3, the placement is transformed to a row based layout style by a timing-driven row assignment method. We have implemented the proposed method on a 4CPU multi-processor workstation and showed that the proposed method is promising through experimental results. I INTRODUCTIONIn recent years, performance of integrated circuits becomes higher and operation speed of logic circuits becomes faster.Hence, for high performance VLSI chips, the interconnection delay is much longer than the gate delay, and it is a major part of whole signal delay of chips. Therefore timing-driven layout methods which take interconnection delay into account explicitly, have been urged to be developed.There have been many studies about timing-driven placement, and they can be classified into the following four approaches, (1) the net weighting approach [l, 3,15,17,20], (2) the net delay bounds approach [6,9,10, 16,211, (3) the path weighting approach [8,22], and (4) the path delay bounds approach [2,7,11,12,19]. However, many of them have a difficulty of trade-off between the quality of the layout and the computation time. Especially for interconnection delay, the estimation of the interconnection delay is inaccurate because of some simplified assumptions of the delay model. Then, we have proposed a timing-driven placement method, called POPINS2.0 [13], which is based on the path delay bounds approach and adopted the delay estimation model based on Elmore's delay model. Experimental results have showed the effectiveness of POPINS2.0. However, in the case of VLSIs which have so much cells in one chip, the computation time of this placement method increased, because of the iterative improvement phase based on nonlinear programming and the row assignment phase based on linear assignment.In this paper, we propose a parallel algorithm for timingdriven placement, which is an extension of POPINS2.0. To obtain high efficiency of parallel processing, we restrict the amount o f communication among processors as much as possible by partitioning the placement problem into some subproblems which can be executed independently. The proposed algorithm consists of three phases. First, we get an initial placement by a hierarchical timing-drivcn mincut placement algorithm. At th...

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Section: Introductionmentioning

confidence: 99%

Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs

Koide

Ono²,

Wakabayashi³

et al.

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

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show abstract

“…There have been many studies about performancle driven layout, especially performance driven placement, and they can be classified into the following four groups, (1)the net weighting approach [2,15], (2)the net delay constraint approach [7,10, 181, (3)the path weighting approach [9,191, and (4:)the path delay constraint approach [3,8, l l , 171. However, many of them have a difficulty of trade-off between the quality of the layout and the computation time.…”

Section: Introductionmentioning

confidence: 99%

A new performance driven placement method with the Elmore delay model for row based VLSIs

Koide

Ono

Wakabayashi

et al.

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 With EDA Technofair

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In this paper, we present a new performance driven placement method based on path delay constraint approach for large standard cell layout. The proposed method concrists of three phases and uses the Elmore delay model to model interconnection delay precisely in each phase. In the first phase, initial placement is performed by an efficient performance driven mincut partitioning method. Next, an iterative improvement method by nonlinear programming improves the layout. The improvement is formulated as the problem of minimizing the total wire length subject to critical path delays. Finally, row assignment considering timing constraint is performed. From the experimental results comparing with RITUAL[17], the proposed method is much, better than RITUAL in point of the maximal violation ratio, the total wire length, and the cut size, and is more effective in point of the interconnection delay model and its extendability.

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A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement

Chandy

Banerjee

1999

Journal of Parallel and Distributed Computing

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A new placement algorithm minimizing path delays

Cited by 9 publications

References 9 publications

Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs

Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs

A new performance driven placement method with the Elmore delay model for row based VLSIs

A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement

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