A New Phenomenon of Retention Time Evolution in Embedded DRAM Technology with High-K Dielectrics (Ta2O5) MIM Capacitor After HTOL Test

Abstract

In this paper, a new phenomenon regarding to failure bit count (FBC) distribution and data retention time of embedded DRAM with high-K dielectric Ta2O5 MIM capacitors has been observed and explored. Different from conventional knowledge with FBC increase or retention time reduction of DRAM after burn-in, it is found FBC decreased and retention time increased in the sub-0.1um embedded DRAM technology with high-K dielectric Ta2O5 MIM capacitors. Although the band-to-defect tunneling (BDT) induced junction leakage currents of cell transistors under hot carrier injection (HCI) and off-state bias-temperature (BT) stress will be enhanced, which degrade the FBC and retention time performance. However, it was found the leakage current reduction of high-K dielectric Ta2O5 capacitor after burn-in dominates the FBC reduction and retention time increase.