A new non-restoring square root algorithm and its VLSI implementations

Fast bit-accurate reciprocal square root

“…One approach for meeting this requirement consists of having architectures with a simple structure that runs at high clock frequency, and the high throughput is achieved by pipelining the algorithm. For this approach, the FxP SR algorithm proposed in [11] is the simplest and most cited option. For the division operation, on the other hand, the coordinate rotation digital computer (CORDIC) is the approach that is most often referenced [15].…”

“…For the division operation, on the other hand, the coordinate rotation digital computer (CORDIC) is the approach that is most often referenced [15]. The FxP SR approach in [11], with a word length input of k bits, will produce a result with a length of k bits after k iterations. CORDICs with a word length input of k bits also produce a result of k bits after k iterations.…”

“…The original SR implementation in [11] has been modified in this paper to produce a final result of k bits while being bit-accurate. To achieve this modification, the iterations must be increased to k þ 1 and the least significant bit is used for rounding the result.…”

“…In the case of the pipelined implementation, the amount of hardware required is significantly increased. In order to compare the proposed algorithm with the straightforward approach, the architecture presented in [11] has been selected for the implementation of the SR algorithm while the CORDIC for the division algorithm, hereafter referred to as concatenated RSR (CRSR). This choice is based on the fact that this approach represents the extreme case of a very fast and simple architecture with few iterations.…”

“…The straightforward FxP RSR implementation consists of a concatenated approach, where a square root (SR) operation is first performed and then a divider is employed. In this context, the research in the open literature has been oriented to the efficient implementation of the separate SR and divider modules; see for instance: [11][12][13][14] for FxP SR and [15][16][17] for FxP division.…”