A new methodology to implement the AES algorithm using partial and dynamic reconfiguration

Granado-Criado, José M.; Vega‐Rodríguez, Miguel A.; Sánchez‐Pérez, Juan M.; Gómez–Pulido, Juan A.

doi:10.1016/j.vlsi.2009.05.003

Cited by 90 publications

(30 citation statements)

References 22 publications

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“…There are a number of studies [17,18,19] that have focused on the performance improvement of this algorithm by using parallelization of its execution.…”

Section: Performance Improvementmentioning

confidence: 99%

Algorithm Aes - Structure, Transformations and Performance

Damjanović¹

2017

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Today' s cryptographic algorithms are designed in a way that they combine m athem atical theory and practice o f computer science in order to improve resistance to cryptanalysis. Cryptographic algorithms are designed around the binary data form at keeping in mind the presumption o f hardening possibility o f cracking the algorithm. One o f the algorithms whose resistance to cryptanalysis during the past 16 years is extensively tested algorithm AES. The Advanced Encryption Standard (AES) is the first cryptographic standard aroused as the result o f public competition established by U.S. National Institute o f Standards and Technology (NIST). AES has emerged as restriction on winner o f this com petition, called Rijndael algorithm on the block size o f 128 bits. From the moment o f its acceptance o f the standard in

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“…There are a number of studies [17,18,19] that have focused on the performance improvement of this algorithm by using parallelization of its execution.…”

Section: Performance Improvementmentioning

confidence: 99%

Algorithm Aes - Structure, Transformations and Performance

Damjanović¹

2017

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“…its disadvantage. The next method is considered in [3,5,8,13,20,35,36] where various kind of memories such as ROMs, 5 BRAMs, 6 and LUTs 7 are used to implement the table of S-box. This method can reduce the area cost; however it suffers from unbreakable delay of memories that leads to a reduction in throughput.…”

Section: Introductionmentioning

confidence: 99%

“…Cell array reconfigurable architecture is proposed in [24] which provides a high-efficiency, low-hardware overhead and high reliability in AES. By combining the use of three hardware languages (Handel-C, VHDL, and JBits), a new methodology is presented in [20] where authors employed dynamic and partial reconfiguration with parallelism and pipelining to implement AES. In the other words, in [20], authors used VHDL for implementation of AES elements and Handel-C for implementation of the communication system.…”

Section: Introductionmentioning

confidence: 99%

“…By combining the use of three hardware languages (Handel-C, VHDL, and JBits), a new methodology is presented in [20] where authors employed dynamic and partial reconfiguration with parallelism and pipelining to implement AES. In the other words, in [20], authors used VHDL for implementation of AES elements and Handel-C for implementation of the communication system. A group of works in the literature deals with designing low cost and low power consumption FPGA-based schemes for implementation of AES [48,49].…”

Section: Introductionmentioning

confidence: 99%

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An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

Soltani

Sharifian

2015

Microprocessors and Microsystems

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“…The AES hardware implementations provide the highest speed for the real-time applications [3]. Many researches have been recently done on different hardware implementations, using ASIC [4,5] and FPGA technologies [3,6].…”

Section: Introductionmentioning

confidence: 99%

Design of a Specific Instructions Set Processor for AES Algorithm

Shahbazi¹,

Eshghi²

2014

IJCA

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In this paper, a new architecture for Advanced Encryption Standard (AES) Algorithm based on Application Specific Instruction set Processors (ASIP) design technique is proposed. The basic configuration is developed in order to reduce the execution clock pulses for the main specific instructions. According to the improvement of the first register configuration, two ASIPs are designed for AES algorithm. The second ASIP is 89% faster and have 22% less gates than the first proposed design.

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A new methodology to implement the AES algorithm using partial and dynamic reconfiguration

Cited by 90 publications

References 22 publications

Algorithm Aes - Structure, Transformations and Performance

Algorithm Aes - Structure, Transformations and Performance

An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

Design of a Specific Instructions Set Processor for AES Algorithm

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