A New Method to Reduce the Side-Channel Leakage Caused by Unbalanced Capacitances of Differential Interconnections in Dual-Rail Logic Styles

Quan, Jianping; Bai, Guoqiang

doi:10.1109/itng.2009.185

Cited by 3 publications

(1 citation statement)

References 13 publications

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“…In particular, the protection against SCA should be built-in in every custom design of digital cell. The cryptographic method chosen for the design of these cells is known as the No Short-circuit current Dynamic Differential Logic (NSDDL) method [8]. Our goal here is to characterize a two-to-one multiplexer (MUX2x1) cell designed with a good SCA resistance using as little hardware as possible.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of Resistance to Sca for Different Architectures of Encrypted Cell

2020

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This paper deals with a top down design of an example multiplexer cell that exhibits high immunity to Side Channel Attack (SCA). Four different solutions of the encrypted multiplexer cell are revised, and the best design adopted. The post-layout simulations prove resistance of the multiplexer logic cell to the SCA. Since the physical layout structure and the functionality of this kind of design is based on symmetry, concerns were expressed as to what will be the effectiveness of the method under real production conditions. To get a proper answer to that, the adequacy of the chosen design for the multiplexer cell, which uses the "No Short-circuit Current Dynamic Differential Logic" (NSDDL) method, is confirmed by observing a Normalized Standard Deviation (NSD).

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Section: Introductionmentioning

confidence: 99%

Evaluation of Resistance to Sca for Different Architectures of Encrypted Cell

2020

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Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors

Giacomin

Gaillardon

2018

2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

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Hardware Reduction and Statistical Verification of Cryptographic Standard Cell Resistant to SCA

Mirković¹,

Milic

Mirković

et al. 2019

J CIRCUIT SYST COMP

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This paper presents results regarding the progress achieved in the design of a customized encrypted multiplexer cell. The focus of our interest is the no short-circuit dynamic differential logic method that demonstrates high immunity of a standard logic cell to the side channel attacks (SCAs). Three innovative solutions are examined and the best one is proposed for the encrypted multiplexer cell. Designed cells are realized to the layout masks level targeting the 350[Formula: see text]nm CMOS process. The post-layout simulations showed high resistivity to the SCA for all designed cells. The resistance to the SCA of the proposed design was statistically verified at the transistor level. The verification is performed using the Monte Carlo (MC) simulation in which widths and lengths of the transistor channel were varied according to the Gaussian distribution. The designed encrypted cell will be the part of a more complex crypto system for power consumption metering which should increase overall system’s data security.

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A New Method to Reduce the Side-Channel Leakage Caused by Unbalanced Capacitances of Differential Interconnections in Dual-Rail Logic Styles

Cited by 3 publications

References 13 publications

Evaluation of Resistance to Sca for Different Architectures of Encrypted Cell

Evaluation of Resistance to Sca for Different Architectures of Encrypted Cell

Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors

Hardware Reduction and Statistical Verification of Cryptographic Standard Cell Resistant to SCA

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