A new method of power analysis of Network-on-Chip using analytical modelling

Bhaskar, A. Vijaya

doi:10.1109/pdgc56933.2022.10053136

Cited by 2 publications

(2 citation statements)

References 18 publications

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“…In response to the challenges posed by System-on-Chip (SoC) architectures, a novel solution known as network-onchip (NoC) has emerged as a groundbreaking standard for facilitating inter-chip communication within extensive VLSI systems, as highlighted in the work by Bhaskar [1]. This innovative concept of NoC adopts a multi-layered approach that effectively mitigates the complexities associated with design while concurrently enabling the seamless distribution of data.…”

Section: Introductionmentioning

confidence: 99%

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network

Ahmed,

Ambudka,

Yadav

2024

ISI

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The Network-on-Chip (NoC) stands as a potent solution for achieving heightened performance, efficient communication, and dependability in the migration of Very-Large Scale Integration (VLSI) architecture toward deep submicron technology, when contrasted with conventional connectivity networks. Considerable research endeavours have been allocated to diverse facets of NoCs, encompassing topology, routing algorithms, traffic behaviours, power management, and fundamental mapping. This paper explores the power consumption efficiency of Parameterized Path-Based, Randomized, Oblivious, Minimal for 3D Mesh (PROM3D) routing and ZXY routing algorithms for various traffic patterns like transpose, bit shuffle, and random traffic with the help of the integrated DSENT network model. The PROM3D routing algorithm selects a path randomly from all possible minimal pathways between the source and destination, whereas ZXY is a layer-based routing method. The Design Space Exploration of Network (DSENT) tool is used with the NoC Interconnect Routing and Applications Modeling (NIRGAM) simulator in experiments to measure the power consumption. The findings indicate that, within the 3D-Mesh environment, the ZXY routing algorithm exhibits a 0.02% of variation in power consumption while in saturation on varying loads for various traffic patterns in comparison to the PROM3D algorithm.

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Section: Introductionmentioning

confidence: 99%

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network

Ahmed,

Ambudka,

Yadav

2024

ISI

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“…A range of parameters, including area, throughput, latency, and power consumption, can measure the SoC's performance, which directly impacts the system's performance [8,9]. The modified Fat-Tree topology proposed in this paper reduces memory requirements in intermediate nodes, thus lowering power consumption [10,11].…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

Yadav,

Ahmed,

Ambudkar

et al. 2023

MMEP

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The rapid evolution of integration technology has significantly influenced System-on-Chip (SoC) design, characterized by the unprecedented integration of numerous functional modules onto ever-shrinking chips. Consequently, facilitating robust communication between these burgeoning modules has become critical to optimizing system functionality and performance. Traditional Bus architecture, however, proves inadequate in realizing this goal. To circumvent these communication impediments, mesh and torus interconnected architectures have been proposed, with cores interconnected within a single chip using diverse routing strategies for seamless operation. This study investigates a deterministic, deadlock-free routing protocol for a modified Fat-Tree topology that incorporates a core module at the intermediate level.Utilizing the Sniper simulator environment for evaluation, it is demonstrated that the proposed protocol surpasses the X-Y routing method used in both mesh and torus topologies in terms of power efficiency and throughput. The results show a 4%-8% reduction in power consumption compared to other approaches, indicating the superior efficacy of the proposed method.

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A new method of power analysis of Network-on-Chip using analytical modelling

Cited by 2 publications

References 18 publications

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

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