A new method for concurrent checking by use of a 1-out-of-4 code

Goessel, M.; Saposhnikov, Vl. V.; Дмитриев, Антон Леонидович; Saposhnikov, V.

doi:10.1109/olt.2000.856627

Cited by 13 publications

(9 citation statements)

References 5 publications

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“…In general for these methods the area overhead is high, the delay may increase and in same cases the latency of error detection also increases. Recently a new method for concurrent checking by use of complementary circuits was introduced [3], [10]. In this paper we show under which conditions totally self-checking circuits can be designed by use of this new method.…”

Section: Introductionmentioning

confidence: 92%

“…In this chapter we shortly recapitulate the method of error detection by use of complementary circuits as introduced in [3], [10]. Fig.…”

Section: Error Detection By Complementary Circuitsmentioning

confidence: 99%

“…The utilization of these degrees of freedom for an optimal synthesis of the complementary circuit g is a challenging problem which was solved to some extend for a 1-out-of-4 code, a Berger code and a 1-out-of-3 code in [3], [10], [11]. For the general case it remains an open problem.…”

Section: Error Detection By Complementary Circuitsmentioning

confidence: 99%

See 2 more Smart Citations

Necessary and sufficient conditions for the existence of totally self-checking circuits

Saposhnikov¹,

Saposhnikov²,

Morozov³

et al. 2004

Proceedings. 10th IEEE International on-Line Testing Symposium

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Section: Introductionmentioning

confidence: 92%

“…In this chapter we shortly recapitulate the method of error detection by use of complementary circuits as introduced in [3], [10]. Fig.…”

Section: Error Detection By Complementary Circuitsmentioning

confidence: 99%

See 1 more Smart Citation

Necessary and sufficient conditions for the existence of totally self-checking circuits

Saposhnikov¹,

Saposhnikov²,

Morozov³

et al. 2004

Proceedings. 10th IEEE International on-Line Testing Symposium

Self Cite

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show abstract

“…T OTALLY self-checking (TSC) circuits [7], [2] (defined in §2) guarantee correct output until they signal an error, under certain fault assumptions. Some self-checking circuit synthesis techniques (Table 1) sometimes produce TSC circuits [49], [9], [19], [36], [10] while others offer partial fault coverage [11], [13], [20], [18], [38]. Some add concurrent error detection (CED) without requiring modifications to the original circuit (ie.…”

Section: Introductionmentioning

confidence: 99%

Automatic Synthesis of Totally Self-Checking Circuits

Garvie,

Husbands

2019

Preprint

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Totally self-checking (TSC) circuits are synthesised with a grid of computers running a distributed population based stochastic optimisation algorithm. The presented method is the first to automatically synthesise TSC circuits from arbitrary logic as all previous methods fail to guarantee the checker is self-testing (ST) for circuits with limited output codespaces. The circuits synthesised by the presented method have significantly lower overhead than the previously reported best for every one of a set of 11 frequently used benchmarks. Average overhead across the entire set is 23% of duplication and comparison overhead, compared with an average of 69% for the previous best reported values across the set. The methodology presented represents a breakthrough in concurrent error detection (CED). The highly efficient, novel designs produced are tailored to each circuit's function, rather than being constrained by a particular modular CED design methodology. Results are synthesised using two-input gates and are TSC with respect to all gate input and output stuck-at faults. The method can be used to add CED with or without modifications to the original logic, and can be generalised to any implementation technology and fault model. An example circuit is analysed and rigorously proven to be TSC.

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“…Automatic synthesis methods for totally self-checking (TSC) with less than duplication overhead have been proposed (see, e.g., [14], [5], [3], [4]). Garvie has presented a method capable of adding logic around an unmodified original output generating function circuit to make it TSC with less than duplication overhead.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

Sekanina

2007

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

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This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detect a reasonable number of stuck-at-faults without the need of any additional logic and diagnostic signals. A fault is indicated by oscillations at the carry-out output. Properties of n-bit carrypropagate adder which is composed of the proposed 1-bit selftesting adders are investigated.

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A new method for concurrent checking by use of a 1-out-of-4 code

Cited by 13 publications

References 5 publications

Necessary and sufficient conditions for the existence of totally self-checking circuits

Necessary and sufficient conditions for the existence of totally self-checking circuits

Automatic Synthesis of Totally Self-Checking Circuits

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

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