A new low-leakage T-Gate based 8T SRAM cell with improved write-ability in 90nm CMOS technology

Pasandi, Ghasem; Qasemi, Ehsan; Fakhraie, S.M.

doi:10.1109/iraniancee.2014.6999569

Cited by 11 publications

(8 citation statements)

References 10 publications

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“…The remaining 6T portion of the cell is optimized [7] for writing operation, resulting in overall lower Vmin voltage.A Separated data retention element and data output element means that there will be no correlation between the read SNM Cell and l. Thus, an 8TSRAM design [7] contains a write assist in which a horizontally routed VDD line is collapsed as showed in the fig 4. The Fig.5 shows that 8T SRAM bit cell is designed with two sleep mode transistors, connected as pull down mode transistors [7] to achieve low power design mode and to avoid the static noise margin. To write data '1' into SRAM cell the WL is asserted and BL is made high and BLB is low.…”

Section: T Sram Cellmentioning

confidence: 99%

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Design & Implementation of Subthreshold Memory Cell design based on the primary constraints

Reddy¹

2017

IOSR JVSP

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Section: T Sram Cellmentioning

confidence: 99%

“…[13] Proposed Architecture is designed using Schmitt trigger-based 8T SRAM bit cell illustrated in Fig.[7]. It is similar to the standard 6T SRAM cell, however it is used High-V th nMOS in this design [7]. Two sleep transistors are used in pull down path to minimize the leakage power [15].…”

Section: Proposed Sram Architecture Schmitt Trigger-based Sub-vt 8t Smentioning

confidence: 99%

Design & Implementation of Subthreshold Memory Cell design based on the primary constraints

Reddy¹

2017

IOSR JVSP

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“…Aly et.al [9] Zhai et.al [6] Kim et.al [8] Wen et.al [24] SRAM Cell Verma et.al [21] Change et.al [17] Islam et.al [18] Liu et.al [16] Takeda et.al [13] Saeidi et.al [14] Pasandi et.al [3], [5], [10], [25] Read Stability & write enhanced Fig. 1: Tree diagram for different SRAM cells based on the improvement they suggest.…”

Section: Our Proposed Designmentioning

confidence: 99%

A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations

Pasandi

Fakhraie

2015

IEEE Trans. VLSI Syst.

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In this paper, we present a new 9T SRAM cell that has good write ability and improves read stability at the same time. Simulation results show that the proposed design increases read static noise margin and I ON /I OFF of read path by 219% and 113%, respectively, at supply voltage of 300-mV over conventional 6T SRAM cell in a 90-nm CMOS technology. The proposed design lets us reduce the minimum operating voltage of SRAM (VDD min ) to 350 mV, whereas conventional 6T SRAM cannot operate successfully with an acceptable failure rate at supply voltages below 725 mV. We also compared our design with three other SRAM cells from recent literature. To verify the proposed design, a 256-kb SRAM is designed using new 9T and conventional 6T SRAM cells. Operating at their minimum possible V DDs , the proposed design decreases write and read power per operation by 92% and 93%, respectively, over the conventional rival. The area of the proposed SRAM cell is increased by 83% over a conventional 6T one. However, due to large I ON /I OFF of read path for 9T cell, we are able to put 1k cells in each column of 256-kb SRAM block, resulting in the possibility for sharing write and read circuitries of each column between more cells compared with conventional 6T. Thus, the area overhead of 256-kb SRAM based on new 9T cell is reduced to 37% compared with 6T SRAM.

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“…Recently, several designs for SRAM have been introduced to solve the operational challenges of the conventional 6T SRAM cell at low supply voltages. Some of these designs focus on increasing the writeability of the SRAM cell by weakening the positive feedback of the cell during the write operation [13][14][15], by increasing the strength of the write access transistor (using wider transistors for the write access) [16] or by applying higher voltages to the gate of the access transistors during the write operation. On the other hand, some other designs focus on increasing the read static noise margin (RSNM) to tackle the problem of low RSNM, which is one of the main operational challenges of the conventional 6T SRAM at low supply voltages.…”

Section: Introductionmentioning

confidence: 99%

Low‐power data encoding/decoding for energy‐efficient static random access memory design

Pasandi

Mehrabi

Ebrahimi

et al. 2019

IET Circuits, Devices & Systems

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This study presents a new energy-efficient design for static random access memory (SRAM) using a low-power input data encoding and output data decoding stages. A data bit reordering algorithm is applied to the input data to increase the number of 0s that are going to be written into the SRAM array. Using SRAM cells which are more energy-efficient in writing a '0' than a '1' benefits from this, resulting in a reduction in the total power and energy consumptions of the whole memory. The input data encoding is performed using a simple circuit, which is built of multiplexers and inverters. After the read operation, data will be returned back to its initial form using a low-power data decoding circuit. Simulation results in an industrial and a predictive CMOS technology show that the proposed design for SRAM reduces the energy consumption of read and write operations considerably for some standard test images as input data to the memory. For instance, in writing pixels of Lenna test image into this SRAM and reading them back, 15 and 20% savings are observed for the energy consumption of write and read operations, respectively, compared with the normal write and read operations in standard SRAMs.

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A new low-leakage T-Gate based 8T SRAM cell with improved write-ability in 90nm CMOS technology

Cited by 11 publications

References 10 publications

Design & Implementation of Subthreshold Memory Cell design based on the primary constraints

Design & Implementation of Subthreshold Memory Cell design based on the primary constraints

A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations

Low‐power data encoding/decoding for energy‐efficient static random access memory design

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