A New Lightweight and High Fault Tolerance Sobel Edge Detection Using Stochastic Computing

Abstract

Abstract:A new Stochastic Computing (SC) circuit design paradigm for image processing system is presented in this work. Two improved SC computational functions are derived, which are namely the stochastic scaled addition and stochastic absolute value of difference. Data correlation is also incorporated in the design for effective circuit size reduction without imposing accuracy degradation in the hardware implementations. The proposed SC functions are next employed to design the new and lightweight Sobel edge detection. Experimental results obtained from detailed test analysis have proven that new implementation has satisfactory accuracy level and higher fault tolerance capability in comparison with their conventional counterparts. The works proposed are also implemented on an Altera Cyclone V 5CGXFC7D6F31C6 FPGA for hardware complexity evaluation.

Low area and high throughput implementation of advanced encryption standard hardware accelerator on FPGA using Mux‐Demux pair

“…Table 1 compares the outlined schemes in the given research papers on the basis of the logic elements being used. A minimum area of 2059 slices is obtained by four stage pipelining of S‐box 5 which is implemented on Cyclone IVE. The 32‐bit datapath encryption method 7 covers an area of 2106 slices on TCMS 65 nm technology, while it was 2444 slices for a non‐pipelined style of implementation on Virtex‐7 18 .…”

“…It is ideal for both software and hardware applications that require low latency and good throughput as it is a highly secure algorithm due to usage of longer key lengths, enabling faster encryption. However, AES still needs attention for optimizing the algorithm further by establishing a trade-off between various parameters like area and throughput 4 ; rate of operation and area 5 ; speed and capacity 6 ; energy and power consumed 7 ; and finally data security and area. 8 In this paper, area metric is considered for optimization to reduce the size of processor on which the current AES is implemented.…”

“…The research study by Wong et al 5 compares six different architectures of S‐box, targeting high performance and lightweight applications. An implementation of 4‐stage pipelined Composite Field S‐box is presented.…”

Comparative Study in Enhancing AES Algorithm: Data Encryption

“…(Latifi) The following activities are required: SubByte transformation: AES uses 128-bit data blocks; therefore, each database item is 16 bytes. The Rijndael S-box, which has an 8-bit resolution, is used to turn each data record entity into a distinct type of data (Wong et al, 2018). First, the data in the remaining three rows of the state are shifted from one cycle to another using the ShiftRows transformation.…”