A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits

Garbolino, T.; Hlawiczka, A.

doi:10.1007/3-540-48254-7_22

Cited by 13 publications

(9 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As a consequence, sequences of test vectors produced by such a register must not be considered as fully pseudo-random ones, both for the test-per-scan and test-per-clock testing strategies [10,40]. Similar observations are reported in [38] with respect to poor randomness of test vectors sequences delivered at outputs of a conventional LFSR.…”

Section: Examplementioning

confidence: 79%

“…177-181), [12,[34][35][36][37]. In addition, page 322 in [38] shows an example to demonstrate that test vector sequences generated by an I-type LFSR and feeding parallel inputs of a circuit tested in the test-per-clock mode shall be incapable of detecting some faults in the digital circuit under test.…”

Section: Examplementioning

confidence: 99%

“…The engineering concept disclosed in this chapter is based on the application of DT-LFSR (Linear Feedback Shift Register composed of D-and T-type flip-flops) shift registers with a linear feedback [38,59] to new types of pseudo-random TPGs for LBIST circuits with the STUMPS architecture. However, before the structure of the innovative TPG is revealed, let us outline some selected properties of DT-LFSR registers.…”

Section: New Approach To Engineering Of Pseudo-random Pattern Generators For Lbist Circuits With the Stumps Architecturementioning

confidence: 99%

See 2 more Smart Citations

A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

Garbolino

2021

Applied Sciences

Self Cite

View full text Add to dashboard Cite

Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT‑LFSR‑TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.

show abstract

Section: Examplementioning

confidence: 79%

Section: Examplementioning

confidence: 99%

Section: New Approach To Engineering Of Pseudo-random Pattern Generators For Lbist Circuits With the Stumps Architecturementioning

confidence: 99%

See 1 more Smart Citation

A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

Garbolino

2021

Applied Sciences

Self Cite

View full text Add to dashboard Cite

show abstract

“…The proposed LFSR structures are based on D-type flip-flops, while in recent years LFSR composed of D-type and T-type flip-flops or even of T-type flip-flops only, has been gaining popularity. The main reason is its low area overhead and high operating speed (Garbolino & Hlawiczka, 1999;Garbolino et al, 2000). Some applications of such a type of LFSRs can be found in (Garbolino & Hlawiczka, 2002;Garbolino & Papa, 2008;Novák et al, 2004).…”

Section: Introductionmentioning

confidence: 99%

Stochastic Approach to Test Pattern Generator Design

Papa¹

2011

Stochastic Optimization - Seeing the Optimal for the Uncertain

Self Cite

View full text Add to dashboard Cite

“…Mostly, the proposed LFSR structures are based on Dtype flip-flops, while in recent years LFSR composed of Dtype and T-type flip-flops or the one containing solely Ttype flip-flops is gaining popularity due to its low area overhead and high operating speed [17,19]. Some applications of such a type of LFSRs can be found in [18,20,33].…”

mentioning

confidence: 99%

Genetic algorithm for test pattern generator design

Papa

2010

Appl Intell

Self Cite

View full text Add to dashboard Cite

The paper describes an approach for the generation of a deterministic test pattern generator logic, which is composed of D-type and T-type flip-flops. This approach employs a genetic algorithm that searches for an acceptable practical solution in a large space of possible implementations. In contrast to conventional approaches the proposed one reduces the gate count of a built-in self-test structure by concurrent optimization of multiple parameters that influence the final solution. The optimization includes the search for: the optimal combination of register cells type; the presence of inverters at inputs and outputs; the test patterns order in the generated test sequence; and the bit order of test patterns. Results of benchmark experiments and comparison with similar studies demonstrate the efficiency of the proposed evolutionary approach.

show abstract

A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits

Cited by 13 publications

References 4 publications

A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

Stochastic Approach to Test Pattern Generator Design

Genetic algorithm for test pattern generator design

Contact Info

Product

Resources

About