A new latch-based threshold logic family

Padure, M.; Cotöfană, Sorin; Cogălniceanu, Dan; Bodea, Mircea; Vassiliadis, S.

doi:10.1109/smicnd.2001.967522

Cited by 16 publications

(6 citation statements)

References 9 publications

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“…This property has attracted researchers' attention for decades and resulted in many threshold logic implementations (surveyed in [2]). Among them, those based on CMOS differential logic show the greatest promise in terms of speed, power, and area [4,6,10]. The principle of threshold function computation in these circuits is sensing the difference in the effective impedances between two networks of parallel transistors.…”

Section: Threshold Logicmentioning

confidence: 99%

A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS

Leshner

Berezowski

Yao

et al. 2010

2010 IEEE Computer Society Annual Symposium on VLSI

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In this paper we describe the design, simulation, fabrication, and test of a 32-bit 2's complement integer multiplier constructed from a combination of CMOS standard cells and threshold logic elements in a 65 nm low power process. As compared to a multiplier designed solely using CMOS standard cells, the threshold logic based multiplier is 1.23x smaller and consumes 1.41x less dynamic power and 2.5x less leakage power at the same process corner.

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Section: Threshold Logicmentioning

confidence: 99%

A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS

Leshner

Berezowski

Yao

et al. 2010

2010 IEEE Computer Society Annual Symposium on VLSI

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“…34 shows its schematic for a generic pull-down tree and the circuit structure for an -input MAJORITY gate. • Differential current-switch threshold logic (DCSTL) [164]- [166] (Fig. 35) after the DCSL [168], [169].…”

Section: Differential Solutionsmentioning

confidence: 99%

VLSI implementations of threshold logic- a comprehensive survey

Beiu

Quintana

Avedillo

2003

IEEE Trans. Neural Netw.

193

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This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

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“…Compared to [9] and [8], the circuit in [4] isolates the input networks from the sense-amplifier to increase the conductivity difference. This increases the difference between T and w i , so that an evaluation of the output can be more easily computed.…”

Section: Introductionmentioning

confidence: 99%

Fast and robust differential flipflops and their extension to multi-input threshold gates

Yang

Kulkarni

Davis

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay. We also show a comparison of tolerance against noise and process variation between the different designs. The two proposed designs are found to be as robust as an existing D-flipflop from both commercial standard cell libraries. Meanwhile, they are 33% and 25% faster in 65nm post-layout and 25% and 22% faster in 28nm post-layout compared to a commercial D-flipflop. The energy delay product of two proposed designs is 46% and 25% smaller in the 28nm process post layout simulation. Single input threshold gates can also be extended to multi-input threshold gates. We compare the total delay, power and leakage of a three-input threshold gate as well as a seveninput threshold gate with those of the equivalent (Complementary Metal Oxide Semiconductor) CMOS counterpart, which shows 52% 48% improvement in 65nm and 35% speed improvement in the 28nm process.978-1-4799-8391-9/15/$31.00 ©2015 IEEE

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A new latch-based threshold logic family

Cited by 16 publications

References 9 publications

A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS

A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS

VLSI implementations of threshold logic- a comprehensive survey

Fast and robust differential flipflops and their extension to multi-input threshold gates

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