A new interconnection delay model considering the effects of short-channel logic gates

Abstract

delay t i m e [171. Based upon t h e c o n s i d e r a t i o n s of 1) t h e characteristic-waveform e f f e c t ; 2) t h e i n i t i a l -d e l a y e f f e c t ; 3 ) t h e short-channel (1.5pm) logic-gate e f f e c t s ; 4) t h e pole-zero e f f e c t r a t h e r t h a n t h e p o l e e f f e c t only; and 5) t h e combined l a r g e -s i g n a l e q u i v a l e n t c i r c u i t o f g a t e s and i n t e r c o n n e c t i o n l i n e s , a new modeling approach f o r short-channel CMOS l o g i c g a t e s with i n t e r c o n n e c t i o n l i n e s has been developed. Extensive comparisons between model c a lc u l a t i o n s and SPICE simulations have shown t h a t t h e a n a l y t i c model h a s a maximum e r r o r o f 16% on t h e delay t i m e s f o r CMOS i n v e r t e r s with i n t e r c o n n e c t i o n s o f d i f f e r e n t R and C values and s e c t i o n numbers, and w i t h d i f f e r e n t g a t e s i z e s , device parameters, and even i n p u t e x c i t a t i o n waveforms. Reasonable accuracy, wide a p p l i c a b l e range, and high computation e f f i c i e n c y make t h e developed timing models q u i t e a t t r a c t i v e i n MOS V I S I timing v e r i f i c a t i o n and auto-sizing.

A new and accurate interconnection delay time evaluation in a general tree-type network

“…In MOS integrated circuits, a given logic gate may drive several gates, some of them through long wires whose distributed resistance and capacitance may not be negligible. As device dimensions are scaled down, the interconnection delay among logic gates becomes as important as the logic-gate delay in determining the overall speed performance of a VLSI chip [1,2,3]. The delays caused by interconnection wires are then essential in the evaluation of the switching speed of integrated structures and disregarding them would give completely incorrect results.…”

A new and accurate interconnection delay time evaluation in a general tree-type network

“…As device dimensions are scaled down, the interconnection delay among logic gates becomes as important as the logic-gate delay in determining the overall speed performance of a VLSI chip [1,2,3]. The delays caused by interconnection wires are then essential in the evaluation of the switching speed of integrated structures and disregarding them would give completely incorrect results.…”