A new I-V model considering the impact-ionization effect initiated by the DIGBL current for the intrinsic n-channel poly-Si TFTs

Chen, Hsin-Li; Wu, Chhi‐Chong

doi:10.1109/16.753706

Cited by 12 publications

(4 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This phenomenon is called drain-induced grain barrier lowering (DIGBL) which can largely change the E c profile of SGBs (X = 5 and 0 nm). [29][30][31] The SGB at X = −5 nm can cause the maximum V th variation, because the potential barrier is dominant at the source side.…”

Section: Resultsmentioning

confidence: 99%

Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical silicon–oxide–nitride–oxide–silicon NAND flash memory

Kim

Baek

Lee

2018

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

The effects of single grain boundary (SGB) position and stored electron charges in an adjacent cell in silicon-oxide-nitride-oxide-silicon (SONOS) structures on the variations of threshold voltage (V th ) were investigated using technology computer-aided design (TCAD) simulation. As the bit line voltage increases, the SGB position causing the maximum V th variation was shifted from the center to the source side in the channel, owing to the drain-induced grain barrier lowering effect. When the SGB is located in the spacer region, the potential interaction from both the SGB and the stored electron charges in the adjacent cell becomes significant and thus resulting in larger V th variation. In contrast, when the SGB is located at the center of the channel, the peak position of potential barrier is shifted to the center, so that the influence of the adjacent cell is diminished. As the gate length is scaled down to 20 nm, the influence of stored charges in adjacent cells becomes significant, resulting in larger V th variations.

show abstract

Section: Resultsmentioning

confidence: 99%

Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical silicon–oxide–nitride–oxide–silicon NAND flash memory

Kim

Baek

Lee

2018

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

show abstract

“…The absence of drain current saturation has been commonly observed in poly-Si TFTs. [15][16][17][18][19] Analytical models including grain-boundary barrier lowering 15) or avalanche generation induced by grain boundary defects 16) have been proposed to explain this phenomenon. These models, however, rely on the existence of a potential barrier formed by a grain boundary that is perpendicular to the carrier flow direction.…”

Section: Tft Performancementioning

confidence: 99%

Characterization of High-Performance Polycrystalline Silicon Complementary Metal–Oxide–Semiconductor Circuits

Kawachi¹,

Nakazaki²,

Ogawa³

et al. 2007

jjap

View full text Add to dashboard Cite

Polycrystalline silicon (poly-Si) complementary metal–oxide–semiconductor (CMOS) circuits have been fabricated by using an advanced excimer-laser annealing method and a plasma-oxidation method. The 1-µm-long thin-film transistors (TFTs) were fabricated on arrays of laterally grown long and narrow grains, so that the majority of carriers were free from scattering at grain boundaries during propagation through the channel. The propagation delay time measured by a 21-stage ring oscillator was 175 ps and a power-delay product of 9×10-13 J/gate was obtained at a supply voltage of 3.3 V. The obtained propagation delay time was almost the same as those of bulk Si devices having the same gate length. Furthermore, we expect that 1-µm-long CMOS TFT circuits on glass will have a performance superior to that of 1-µm-long bulk Si devices when the short channel effect and threshold voltage fluctuation are controlled well.

show abstract

“…The drain current keeps increasing even beyond the pinchoff. [1][2][3][4][5][6][7] This feature, the deviation from linear theory, is not favorable for the design of highly integrated circuits with poly-Si TFTs. Thus far, several workers have investigated this nonlinear phenomenon [2][3][4] and have proposed currentvoltage models.…”

Section: Introductionmentioning

confidence: 99%

“…Thus far, several workers have investigated this nonlinear phenomenon [2][3][4] and have proposed currentvoltage models. [3][4][5][6][7] It has been suggested that drain bias induces a decrease in the poly-Si grain boundary (GB) barrier potential, which has been assumed to be nonnegative, [3][4][5][6][7] and this barrier potential decrease causes the drain current increase. [2][3][4] According to this model, nonlinear current ceases to increase when the GB barrier potential disappears.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Grain Boundary Induced Nonlinear Output Characteristics in Polycrystalline-Silicon Thin-Film Transistors

Ikeda¹

2006

jjap

View full text Add to dashboard Cite

We present the two-loop QCD helicity amplitudes for quark-quark and quarkantiquark scattering. These amplitudes are relevant for next-to-next-to-leading order corrections to (polarized) jet production at hadron colliders. We give the results in the 't Hooft-Veltman and four-dimensional helicity (FDH) variants of dimensional regularization and present the scheme dependence of the results. We verify that the finite remainder, after subtracting the divergences using Catani's formula, are in agreement with previous results. We also provide the amplitudes for gluino-gluino scattering in pure N = 1 supersymmetric Yang-Mills theory. We describe ambiguities in continuing the Dirac algebra to D dimensions, including ones which violate fermion helicity conservation. The finite remainders after subtracting the divergences using Catani's formula, which enter into physical quantities, are free of these ambiguities. We show that in the FDH scheme, for gluino-gluino scattering, the finite remainders satisfy the expected supersymmetry Ward identities. JHEP09(2004)039logarithms [4]. There are also sizable uncertainties associated with the experimental input to the parton distribution functions [5]. Nevertheless, an exact next-to-next-to-leading order (NNLO) computation would be desirable. An important step has recently been accomplished with the computation of the three-loop splitting function by Moch, Vermaseren and Vogt [6]. There has also been some earlier work on global fits to the data [7] within an approximate next-to-next-to-leading order (NNLO) framework [8]. Once combined with the matrix elements in complete programs, this should considerably reduce the renormalization and factorization scale uncertainties in production rates. For a summary of the various expected improvements see, for example, ref. [9].Recent years have seen rapid progress in our ability to compute two-loop matrix elements, especially when there is dependence on more than a single kinematic variable [10]-[23]. Much of this progress has relied on new developments in loop integration [24]-[30] and in understanding the infrared divergences of the theory [31].An NNLO calculation of jet production requires six-point tree-level, one-loop fivepoint amplitudes and two-loop four-point amplitudes. The tree amplitudes for six external partons [32,33] and the one-loop amplitudes for five external partons [34] have been determined some time ago. Anastasiou, Glover, Oleari, and Tejeda-Yeomans have provided the NNLO interferences of the two-loop amplitudes with the tree amplitudes, for all QCD four-parton processes, summed over all external helicities and colors [15]. The helicity amplitudes for gg → gg were presented in ref. [18]. Theqq → gg and qg → qg helicity amplitudes were presented in refs. [21,22]. Recently, while preparing this paper, Glover presented the four-quark helicity amplitudes [23]. Here we present the same amplitudes using somewhat different methods, as well as the N = 1 supersymmetric version of these amplitudes. We also describe ambiguities in the...

show abstract

A new I-V model considering the impact-ionization effect initiated by the DIGBL current for the intrinsic n-channel poly-Si TFTs

Cited by 12 publications

References 12 publications

Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical silicon–oxide–nitride–oxide–silicon NAND flash memory

Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical silicon–oxide–nitride–oxide–silicon NAND flash memory

Characterization of High-Performance Polycrystalline Silicon Complementary Metal–Oxide–Semiconductor Circuits

Analysis of Grain Boundary Induced Nonlinear Output Characteristics in Polycrystalline-Silicon Thin-Film Transistors

Contact Info

Product

Resources

About