A new g-boosting design technique for wideband inductorless low-noise transconductance amplifiers

Samavati, Mehdi; Jalali, Mohsen

doi:10.1016/j.mejo.2019.104659

Cited by 5 publications

(6 citation statements)

References 11 publications

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“…Direct G m -enhanced techniques utilize additional devices that control the current passing through the devices to increase the total G m . Examples include adaptive current mirrors [7], negative gain stage [25], and g m -boosting amplifiers [26,27]. Direct g m -boosting techniques generally require additional circuitry with active devices to control the current or amplify the signals.…”

Section: Differential G M -Enhancement Techniquementioning

confidence: 99%

An Ultra-Low-Power 65 nm Single-Tank 24.5-to-29.1 GHz Gm-Enhanced CMOS LC VCO Achieving 195.2 dBc/Hz FoM at 1 MHz

Kurtoglu,

Shirazi,

Mirabbasi

et al. 2024

Electronics

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A low-power single-core 24.5-to-29.1 GHz CMOS LC voltage-controlled oscillator (VCO) is presented. The proposed VCO uses an innovative differential cross-coupled architecture in which an additional pair is connected to the main pair to increase the effective transconductance, resulting in lower power consumption and reduced phase noise (PN). The proposed VCO is fabricated in a 1P9M standard CMOS process and sustains oscillation at 29.14 GHz with power consumption as low as 455 μW (650 μA from a 0.7 V supply), which is ~20% lower than a conventional CMOS LC VCO without Gm-enhanced differential pairs built through the same process (700 μA from 0.8 V supply). When consuming 880 μW (1.1 mA from 0.8 V), the proposed VCO exhibits a tuning range of 4.6 GHz (from 24.5 GHz to 29.1 GHz). Moreover, it exhibits a measured phase noise (PN) better than −106.5 dBc/Hz @ 1 MHz and −132.0 dBc/Hz @ 10 MHz, with figure-of-merit (FoM) results of 195.2 dBc/Hz and 200.3 dBc/Hz, respectively.

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Section: Differential G M -Enhancement Techniquementioning

confidence: 99%

An Ultra-Low-Power 65 nm Single-Tank 24.5-to-29.1 GHz Gm-Enhanced CMOS LC VCO Achieving 195.2 dBc/Hz FoM at 1 MHz

Kurtoglu,

Shirazi,

Mirabbasi

et al. 2024

Electronics

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“…The proposed PGCLNA circuit is depicted schematically in figure 1. The circuit utilizes the g m boosting [14] along with current reuse techniques [15] to accomplish programmable gain control. The PGCLNA consists of two stages: one for programming the gain by considering the received signal power while the other for tuning the gain at the desired frequency range.…”

Section: Circuit Descriptionmentioning

confidence: 99%

“…M 4 -M 6 transistors and load resistor R 1 form the gain splitting stages, connected to the gate of g m boosting transistor M 3 , providing negative feedback gain. The amplified signal applies at the source of M 3 and the gates of M 4 -M 6 at node V 1 , where negative voltage gain is applied to increase the voltage difference across the source and gate of M 3 [14]. The consequence is a boost in transconductance through the application of negative gain on M 3 .…”

Section: Circuit Descriptionmentioning

confidence: 99%

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A novel programmable gain control low noise amplifier (PGCLNA) design for automatic gain control loop in BLE applications

Neeraja,

Khan Md

2024

Eng. Res. Express

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Bluetooth low energy (BLE) is a widely used short-range communication protocol and BLE receivers frequently encounter transient high-power RF (radio frequency) signals from antennas, leading to receiver saturation. To address this issue, this work proposes a 2.4 GHz programmable gain control low-noise amplifier (PGCLNA), which is a key element in an automatic gain control (AGC) system for BLE receiver applications. The proposed PGCLNA achieves discrete levels of gain using the g m -boosting technique by splitting the negative feedback. The proposed circuit is simulated in UMC 180 nm technology and the maximum gain achieved is 41.4 dB, with a step decrease of 15 dB in discrete levels. The gain variations do not degrade the performance of S11, which is always less than -16 dB. The noise figure (NF) is always minimum of 5.5 dB and in high gain mode, the minimum value of NF is 1.82 dB. The third-order intercept point (IIP3) is −7.621 dBm in the best circumstances and always remains above −10.69 dBm. These results are achieved by utilising 5.4 mW power at 1.8 V of supply voltage. The circuit occupies an area of 732 μm × 771 μm. The proposed PGCLNA design offers a solution to accommodate a wide range of input signals in BLE receivers, excellent gain control, low noise and robust performance characteristics, making it an essential component in an AGC system for BLE receiver applications.

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“…The simplest structure of the buffer level is the source follower (SF) [4] , which is shown in Figure 1. Under the premise of negligent bulk effect, it can provide the output impedance of 1/g m [5] , which is relatively small compared with the drain-source resistance r o of MOS transistors, but with the further improvement of integration requirements, the size of MOS transistors is decreasing as well. Under the existing 3.3 V application conditions, the transconductance energy of most non-input MOS transistors is as low as 100 uS, so the value of 1/g m1 is also up to 10 kΩ.…”

Section: Introductionmentioning

confidence: 99%

An Improved Circuit of Super Source Follower Based on g_m-boosting Technology

Yan,

Liu

2023

J. Phys.: Conf. Ser.

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An improved circuit of super source follower (SSF) based on gm-boosting technology is proposed in this paper. The traditional SSF circuit is used to reduce the output impedance of the source follower, to provide stronger load capacity as the output stage of the whole circuit, or to push the non-dominant poles in the multi-stage amplifier circuit to a higher frequency position. In the paper, based on the above SSF circuit, an operational amplifier is connected in parallel between the gate and drain of the Nmos as the feedback loop, which takes the drain as the positive input and the gate as the output to form the gm-boosting structure. The advantage of this structure is to further reduce the output resistance through the voltage-voltage feedback characteristics of the gm-boosting structure. Because two loops are formed after adding the structure, as long as the open-loop gain of the operational amplifier is high enough, the loop formed by the operational amplifier will occupy a dominant position, thus shielding the influence of the source follower on the overall output resistance. The output resistance can change with the operational amplifier gain. The simulation results show that the output impedance of the circuit is only about 92 Ω, which is much lower than 1 kΩ of SSF structure.

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A new g-boosting design technique for wideband inductorless low-noise transconductance amplifiers

Cited by 5 publications

References 11 publications

An Ultra-Low-Power 65 nm Single-Tank 24.5-to-29.1 GHz Gm-Enhanced CMOS LC VCO Achieving 195.2 dBc/Hz FoM at 1 MHz

An Ultra-Low-Power 65 nm Single-Tank 24.5-to-29.1 GHz Gm-Enhanced CMOS LC VCO Achieving 195.2 dBc/Hz FoM at 1 MHz

A novel programmable gain control low noise amplifier (PGCLNA) design for automatic gain control loop in BLE applications

An Improved Circuit of Super Source Follower Based on g_m-boosting Technology

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A new g-boosting design technique for wideband inductorless low-noise transconductance amplifiers

Cited by 5 publications

References 11 publications

An Ultra-Low-Power 65 nm Single-Tank 24.5-to-29.1 GHz Gm-Enhanced CMOS LC VCO Achieving 195.2 dBc/Hz FoM at 1 MHz

An Ultra-Low-Power 65 nm Single-Tank 24.5-to-29.1 GHz Gm-Enhanced CMOS LC VCO Achieving 195.2 dBc/Hz FoM at 1 MHz

A novel programmable gain control low noise amplifier (PGCLNA) design for automatic gain control loop in BLE applications

An Improved Circuit of Super Source Follower Based on gm-boosting Technology

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Product

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An Improved Circuit of Super Source Follower Based on g_m-boosting Technology