A new extraction method for effective channel length on lightly doped drain MOSFET's

Ida, Jiro; Kita, Akio; Ichikawa, F.

doi:10.1109/icmts.1990.67890

Cited by 16 publications

(6 citation statements)

References 4 publications

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“…The reason is that the TED of phosphorus in structure B is larger than that in structure A. Arsenic, which introduces many point defects, enhances the TED of phosphorus. Figure obtained by using a new effective channel length (L&) extraction method [ 151 modified from two other methods [13,14]. Inclusion of HT-RTA introduces a 30 to 40percent decrease of AL.…”

Section: 5mentioning

confidence: 99%

Impact of high‐temperature rapid thermal annealing in deep‐submicrometer CMOSFET design

Shimizu

Ohki

Ishida

et al. 1996

Electron Comm Jpn Pt II

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We investigated the impact of high-temperature rapid thermal annealing (HT-RTA) for CMOSFET design in the deep-submicrometer regime. HT-RTA (>lo00 "C) carried out immediately after ion implantation can reduce the transient enhanced diffusion of implanted impurities and suppress interactions between these impurities, both of which are usually observed in low-temperature furnace annealing processes. HT-RTA is definitely effective in CMOSFET design optimization, since it can control impurity profiles more precisely than conventional thermal processes, leading to improvements in the short-channel effects, current drivability, and reliability of MOSFETs. We also show that HT-RTA serves as a methodology for analyzing the RSCE (reverse short-channel effects) and ESCE (enhanced shortchannel effects) taking place simultaneously in deep-sub-micrometer MOSFETs. 0

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Section: 5mentioning

confidence: 99%

Impact of high‐temperature rapid thermal annealing in deep‐submicrometer CMOSFET design

Shimizu

Ohki

Ishida

et al. 1996

Electron Comm Jpn Pt II

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“…From (8) and Fig. 1, the Le, can be expressed as Note that the uniformity of the interface-trap density along the channel, the source/drain proximity effect, and the sharpness of the effective area edges will be discussed later.…”

Section: Ic M a Z ( Z )mentioning

confidence: 99%

A novel extraction technique for the effective channel length of MOSFET devices

1995

IEEE Trans. Electron Devices

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A novel method using the charge pumping technique for extracting the effective channel length of MOSFET devices is presented, in which the effective area approach is used and the edges of the area are defined clearly. It is shown that the extracted effective channel length is independent of the measuring biases and the proposed new method is simple, accurate, and reliable, as compared to those using the I-V method. With the knowledge of the device dopant profiles, the extracted channel length with 0.01 pm accuracy can he achieved. Moreover, the proposed method is applicable to either n-or p-channel, conventional or LDD, surface or buried channel MOSFET's.

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“…Back then, the semiconductor industry faced a major issue in extracting L eff of MOSFET with LDD. Substantial effort had been put in to overcome this challenge [14][15][16]. In state-of-the-art sub-0.25 µm CMOS technology, the shallow S/D extension is no longer lightly doped but instead heavily doped such that the series resistance is smaller, and a deep conventional diffusion for the S/D is made to allow the use of silicide contact technology without junction spiking.…”

Section: Issues and Limitation Of Current Methods Of L Eff Extraction mentioning

confidence: 99%

“…Since the carrier concentration and, thus the resistance in the lightly-doped regions are strongly dependent on gate bias, the LDD structure make the channel length definition ambiguous. L eff extraction methods suitable for MOS transistors with LDD had been proposed [14][15][16], but will not be discussed in detail in this chapter. Nowadays, the drain/source of sub-0.25 um CMOS technology has a shallow S/D extension, which is no longer lightly doped, and a deep conventional diffusion for the S/D.…”

Section: Limitation Of Current Channel Resistance Methods Of L Eff Extmentioning

confidence: 99%

“…There are basically four different types of approach in extracting L eff electrically, one of the most common approaches is based on the device's I-V characteristics at low drain bias or linear region [14,15,[25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40], the second type of approach is base on the measured C -V data of a series of MOS transistors with different channel lengths [16,[41][42][43][44][45][46][47][48].…”

Section: Electrical Characterization-extraction Of L Effmentioning

confidence: 99%

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Improved effective channel length extraction method for 0.09-0.13 mm CMOS

Eng¹

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13 µm and 0.1 µm CMOS technology. 4.12 I-V characteristics of two NMOS transistors with the same L drawn but different L eff measured by our modified shift-and-ratio method with a Vgs range from 0.2 to 0.5 V , showing that a higher off current and a higher on current correspond to a smaller L eff measured. 4.13 L eff extracted for different Vgs range for 0.13 µm CMOS technology NMOS transistors. V ds was biased at 0.05 V. 4.14 ∆L extracted for different Vgs range for 0.13 µm CMOS technology PMOS transistors. V ds was biased at 0.05 V. 4.15 (a) Variation of L eff in I on-log I off relationship (b) Variation of DIBL in I on-log I off relationship. 4.16 I on versus DIBL for both NMOS and PMOS transistors 4.17 Logarithm of I off versus DIBL for both NMOS and PMOS transistors 4.18 Plot of L eff vs. I off for NMOS transistors fabricated by 0.11 µm CMOS technology. L eff was extracted by MS&R method (0.1-0.5 V V gs range) and also the capacitance method. (Note: CC is correlation coefficient.) 4.19 Plot of L eff vs. I off for NMOS transistors fabricated by 0.11 µm CMOS technology. L eff was extracted by MS&R method at 3 different V gs ranges and also by the S&R method for one V gs range. (Note: CC is correlation coefficient.) 4.20 Plot of L eff vs. I off for PMOS transistors fabricated by 0.11 µm CMOS technology. L eff was extracted by MS&R method (0.1-0.5 V V gs range) and the capacitance method. (Note: CC is correlation coefficient.) 4.21 Plot of L eff vs. I off for PMOS transistors fabricated by 0.11 µm CMOS technology. L eff was extracted by MS&R method for 3 different V gs ranges and also by the S&R method for one V gs range. (Note: CC is correlation coefficient.) 4.22 Plot of I off vs. L eff for NMOS and PMOS transistors fabricated by 90 nm CMOS technology with L gate of 60nm. L eff was extracted by MS&R method (0.1-0.3 V V gs range), (Note: CC is correlation coefficient.) 4.23 Box plot of the measured FICD against various percentages of BARC over-etch trimming.

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A new extraction method for effective channel length on lightly doped drain MOSFET's

Cited by 16 publications

References 4 publications

Impact of high‐temperature rapid thermal annealing in deep‐submicrometer CMOSFET design

Impact of high‐temperature rapid thermal annealing in deep‐submicrometer CMOSFET design

A novel extraction technique for the effective channel length of MOSFET devices

Improved effective channel length extraction method for 0.09-0.13 mm CMOS

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