A new efficient reduction scheme to implement tree multipliers on FPGAs

Mhaidat, Khaldoon; Hamzah, Abdulmughni Y.

doi:10.1109/idt.2014.7038609

Cited by 5 publications

(3 citation statements)

References 12 publications

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“…In [8], the authors have reported comparison of 32‐bit Vedic multiplication with conventional binary multipliers implemented on Xilinx Nexys3 Spartan‐3 FPGA and simulated using the Xilinx simulation platform. In [9], the authors have presented different implementations of a reduction scheme and have implemented tree multipliers by simulation followed by implementation on FPGA platforms. The system implemented was not a binary multiplier system but a reduction scheme for partial product reduction up to a 32‐bit multiplier scheme implemented in Verilog in the Xilinx ISE Suite and targeted on the Xilinx Spartan‐6 platform as hardware.…”

Section: Literature Surveymentioning

confidence: 99%

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Tomar¹,

George

Tomar

2021

IET Circuits, Devices & Syst

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Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as signal processing, video processing and image processing for which floating-point multiplication is an important component. The dynamic range of numbers represented by floating-point arithmetic is very large compared with that of fixed-point numbers of the same bit width. A mantissa similarity investigator (MSI)interfaced multi-precision binary multiplier architecture is developed and can be used in data-intensive applications that require variable precision, high throughput and low delay. This architecture can be configured to operate in single-, double-, quadruple-and octuple-precision modes for mantissa multiplication according to the IEEE 754 standard for floating-point numbers. The system produces increased throughput and utilises mantissa similarity to reduce system delay. The system was synthesised for a variety of field-programmable gate array targets using Xilinx ISE Design Suite 14.7, and performance was simulated using that suite's ISim simulator. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Section: Literature Surveymentioning

confidence: 99%

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Tomar¹,

George

Tomar

2021

IET Circuits, Devices & Syst

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“…They note that both Altera and Xilinx have efficient ternary adders, so they use GPCs to reduce the matrix to three rows. Other work on GPCs that is based on work by Parandeh-Afshar et al presents incremental improvements or additional applications for GPCs [13][14][15]17,20]. Kumm and Zipf present two novel GPCs, (6,0,6;5) and (1,3,2,5;5), that are specific to and optimized for Xilinx FPGAs [19].…”

Section: Related Work: Generalized Parallel Countersmentioning

confidence: 99%

“…They then use ILP to select GPCs to reduce a bit heap to two rows and report improvements over the previous FloPoCo heuristic [19]. Mhaidat and Hamzah [20] present results for a Xilinx Spartan-6 FPGA, which uses a 6-input LUT architecture. They report that their 32 × 32 multiplier uses 1133 LUTs, which is 2.15-times the number used by the proposed multipliers that do not use SRLs and 1.95-times the number used by the proposed n/2 -stage pipelined multipliers that use SRLs.…”

Section: Gpc-based Tree Multipliersmentioning

confidence: 99%

Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs

Walters

2016

Computers

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Abstract:Multiplication is the dominant operation for many applications implemented on field-programmable gate arrays (FPGAs). Although most current FPGA families have embedded hard multipliers, soft multipliers using lookup tables (LUTs) in the logic fabric remain important. This paper presents a novel two-operand addition circuit (patent pending) that combines radix-4 partial-product generation with addition and shows how it can be used to implement two's-complement array multipliers. The circuit is specific to modern Xilinx FPGAs that are based on a 6-input LUT architecture. Proposed pipelined multipliers use 42%-52% fewer LUTs, and some versions can be clocked up to 23% faster than delay-optimized LogiCORE IP multipliers. This allows 1.72-2.10-times as many multipliers to be implemented in the same logic fabric and potentially offers 1.86-2.58-times the throughput by increasing the clock frequency.

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Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization

Tomar¹,

George

2017

Wireless Pers Commun

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A new efficient reduction scheme to implement tree multipliers on FPGAs

Cited by 5 publications

References 12 publications

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs

Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization

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