A new dimension of parallelism in ultra high throughput LDPC decoding

Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications

“…Columns showing default position are (0, 1), (2, 3), (9,12), (11,14) and (13,15). Columns showing non-default position are (4, 5), (6, 7) and (8,10). A red line that goes across 2 Â 2 block is noticeable in case of non-default position in Fig.…”

“…So, it requires a total of 13 þ29 ¼42 comparators coupled with the complex input selection network. The proposed scheme only requires 29 comparators with a very-low-complexity local switch and fixed wired networks 'Odd-Even Split' and 'Odd-Even Combine' as shown in 1 0 [10] sign [11] mag [11] sign [12] mag [12] sign [13] mag [13] sign [14] mag [14] sign [15] mag [15] Fig. 13.…”

“…To meet these demands, multi-gigabit data transmission rate standards, such as IEEE 802.11ad [2] for gigabit wireless local area networks (WLANs) and IEEE 802. 15.3c for wireless personal area networks (WPANs), have been proposed, which have necessitated the implementation of multi-gigabit high-throughput LDPC decoder architectures to meet the continuing demand for ever-higher data rates [5][6][7][8][9][10][11].…”

“…In fact, it shows only 3.45 Gb/s using 65-nm CMOS technology. Schlafer et al [10] designed a decoder for ultrahigh throughput applications. It shows extremely high throughput at the cost of extremely high area.…”

“…Finally, no special low-complexity routing and sorting architecture has been described for multimode applications. The 802.11ad decoders presented by Li et al [9] and Schlafer et al [10] are single-rate (rate-13/16) LDPC decoders, specifically designed for ultra-low-area and ultra-high-throughput applications, respectively. None of these decoders shows any implementation for multi-mode applications.…”