A new diagonal storage for efficient implementation of sparse matrix–vector multiplication on graphics processing unit

He, Gaohong; Chen, Qi; Gao, Jiaquan

doi:10.1002/cpe.6230

Cited by 2 publications

(3 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this section, we describe the method of BRCSD and HDC and analyze the advantages/disadvantages of the two methods. Examples in literature 17 are referred to give an illustration in this section, as shown in Figure 1.…”

Section: Compressed Formatmentioning

confidence: 99%

“…BRCSD introduces the concept of piece point and effectively divides the input matrix into blocks through the piece point array. According to the example in Reference 17, it is assumed that the piece point has been calculated, as shown in Figure 3.…”

Section: Compressed Formatmentioning

confidence: 99%

“…Godwin et al, 16 through studying the application of a technology of block diagonal structure to optimize SpMV on GPU. He et al 17 proposed the RBDCS method according to the characteristics of the matrix of long‐zero diagonals, along which it could cope with different matrix formats whereupon codes could be automatically generated. A higher performance improvement could be seen compared to DIA.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A two‐stage parallel method on GPU based on hybrid‐compression‐format for diagonal matrix

Cui

Wang

Han

et al. 2023

Concurrency and Computation

View full text Add to dashboard Cite

SpMV (Sparse matrix‐vector multiplication) is an important computing core in traditional high‐performance computing and also one of the emerging data‐intensive applications. For diagonal sparse matrices, it is frequently necessary to fill in a large number of zeros to maintain the diagonal structure as for using DIA (Diagonal) storage format. The fact that filling with zeros may consume additional computing and memory resources, will certainly lead to degradation of the parallel computing performance of SpMV, further causing computing and storage redundancy. To solve the deficiencies of the DIA format, a Two‐stage parallel SpMV method is presented in this paper, which can reasonably distribute the data of diagonal matrix and irregular matrix to different CUDA kernels. As different corresponding compression methods are particularly designed for different matrix forms, a partition‐based hybrid format of DIA and CSR (HPDC) is therefore adopted in the two‐stage method to ensure load balancing among computing resources and continuity of data access on the diagonal. Simultaneously, a standard deviation among blocks is used as a criterion to obtain the optimal number of blocks and distribution of data. The experimental data were implemented in the Florida data set. Compared to DIA, cuSPARSE‐CSR, HDC, and BRCSD, the execution time of the Two‐stage method is shortened by 4, 3.4, 1.9, and 1.15, respectively.

show abstract

Section: Compressed Formatmentioning

confidence: 99%

Section: Compressed Formatmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A two‐stage parallel method on GPU based on hybrid‐compression‐format for diagonal matrix

Cui

Wang

Han

et al. 2023

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

Block-wise dynamic mixed-precision for sparse matrix-vector multiplication on GPUs

Zhao,

Zhang,

et al. 2024

J Supercomput

View full text Add to dashboard Cite

Sparse matrix-vector multiplication (SpMV) plays a critical role in a wide range of linear algebra computations, particularly in scientific and engineering disciplines. However, the irregular memory access patterns, extensive memory usage, high bandwidth requirements, and underutilization of parallelism hinder the computational efficiency of SpMV on GPUs. In this paper, we propose a novel approach called block-wise dynamic mixed-precision (BDMP) to address these challenges. Our methodology involves partitioning the original matrix into uniformly sized blocks, with each block’s size determined by considering architectural characteristics and accuracy requirements. Additionally, we dynamically assign precision to each block using a precision selection method that takes into account the value distribution of the original sparse matrix. We develop two distinct SpMV computation algorithms for BDMP: BDMP-PBP (Precision-based partitioning) and BDMP-TCKI (Tailored compression and kernel implementation). BDMP-PBP partitions the matrix into two independent matrices for separate computations based on block precision, offering flexibility for integration with other optimization techniques. Meanwhile, BDMP-TCKI focuses on achieving significant thread-level parallelism and memory utilization by tailoring an appropriate compressed storage format and kernel implementation for each block. We compare BDMP with NVIDIA’s cuSPARSE library and three state-of-the-art SpMV methods, including SELLP, MergeBase, and BalanceCSR, using matrices from the University of Florida’s SuiteSparse dataset collection. BDMP-PBP and BDMP-TCKI show average speedups up to 2.64$$\times $$ × and 2.91$$\times $$ × on Turing RTX 2080Ti, and up to 2.99$$\times $$ × and 3.22$$\times $$ × on Ampere A100. The results demonstrate that BDMP enables the optimization of computation speed without compromising the precision necessary for reliable results.

show abstract

A new diagonal storage for efficient implementation of sparse matrix–vector multiplication on graphics processing unit

Cited by 2 publications

References 19 publications

A two‐stage parallel method on GPU based on hybrid‐compression‐format for diagonal matrix

A two‐stage parallel method on GPU based on hybrid‐compression‐format for diagonal matrix

Block-wise dynamic mixed-precision for sparse matrix-vector multiplication on GPUs

Contact Info

Product

Resources

About