A new design method for imperfection-immune CNFET-based circuit design

Ebrahimi, Seyyed Ashkan; Reshadinezhad, Mohammad Reza; Bohlooli, Ali

doi:10.1016/j.mejo.2019.01.013

Cited by 7 publications

(4 citation statements)

References 24 publications

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“…36 The inverter gate structure based on CNTFET technology is very immune against the challenge of misaligned/mis-positioned for CNTs. 37 Since the inverter gate is a special gate of GAA CNT-GDI, therefore, in the design of blocks of the proposed memory architecture, different functions like NOT, F1, and F2 of GAA CNT-GDI cell were used. Based on Fig.…”

Section: Input Diffusion-terminalsmentioning

confidence: 99%

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

Darabi¹,

Salehi²,

Abiri³

2022

ECS J. Solid State Sci. Technol.

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We propose a novel design of an ultra-low power radiation-hardened single-ended (UPRHSE) SRAM bit-cell using the GAA CNT-GDI method. In the structure of bit-cell to improve read-/hold-stability and expand write-ability several schemes have been used such as asymmetric virtual ground gating, built-in read-assist and the multi-diameter/chirality for CNTs. Also, to investigate single/double upsets, injection circuit model using the structure of the T-connected pseudo resistors is proposed. The results of extensive Monte-Carlo simulations to evaluate the proposed bit-cell indicate larger noise margins, acceptable yield, less sensitivity to PVT variations, and higher critical charge. Moreover, the suggested bit-cell has more robustness to soft errors with high reliability of data storage in the presence of critical voltage conditions, and better results in other comprehensive figures of merit as compared to state-of-the-art bit-cells in the 16 nm technology. Finally, the proposed bit-cell in a real application is used to store data from two-layer quick-response code-based in terrestrial environments. The results show better performance of the bit-cell in terms of a comprehensive FoM, which provides more effective trade-off between the hardware efficiency and quality metrics to evaluate the appropriate accuracy in the pixel-by-pixel image as compared to other well-known counterpart designs.

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Section: Input Diffusion-terminalsmentioning

confidence: 99%

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

Darabi¹,

Salehi²,

Abiri³

2022

ECS J. Solid State Sci. Technol.

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“…Nevertheless, if voltage restoring/driving large capacitor (high fan-out) are required, the NOR, NAND, F 1 , and F 2 structures from the basic GAA CNT-GDI method-based cell structure with reverse cell (NOT gate) must be used, where their output node connect in a cascade form with GAA CNT-GDI cell based-inverter cell for guarantees sufficient drive of the cascaded arbitrarily cells and work reliably increase for any cascade circuit, where these architectures are illustrated in Table 1. Due to the fact that in the inverter cell structures the misaligned/mis-positioned CNTs do not occur [19], and because they are a special case of the GAA CNT-GDI cell, the fundamental logic functions implemented through the proposed cell structure will be very immune against to the challenge of misaligned/mis-positioned CNTs in the manufacturing phase.…”

Section: The Proposed Low-power Rad-hard Se 11-t Sram Bit-cell (Uprhse) and Behavioral Mechanismmentioning

confidence: 99%

“…According to the cause expressed for fabrication phase and since the inverter gate is a special case of GAA CNT-GDI cell with the probability of misaligned/mis-positioned problem of CNTs (short path from output to V dd or GND, i.e. source and drain terminal [19]), so to achieve a memory array circuit design with optimal implementation as well as high drive current and voltage restoring capability structures, body structure design of writing driver/input buffer and sense amplifier (Amp. )/output buffer blocks in the write/read direct paths of the data-bit into the proposed bitcell, according to the functions presented in Table 1, was performed using the F 1 , F 2 and NOT functions of the CNT-GDI GAA cell based on multiple-threshold voltage technique (i.e., multi-CNT diameter/chirality design [20]).…”

Section: The Proposed 1×1 Memory Architecture and Its Peripherals Blocksmentioning

confidence: 99%

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A wrap-gate CNT-MOSFET based SRAM bit-cell with asymmetrical ground gating and built-in read-assist schemes for limited-energy environments application

Darabi

Salehi

Abiri

2021

Preprint

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Today, designing low-power single-bit SRAM structures with the ability to operate regularly at low supply voltages and with high immunity against standard radiation particles impact is challenging for designers. In the present article, a novel design of a low-power radiation-hardened single-ended SRAM bit-cell (UPRHSE) based on gate-diffusion input (GDI) method using gate-all-around carbon nano-tube (CNT) MOSFETs (GAA CNT-MOSFETs) along with dual-chirality/multiple-diameter technique for CNTs with an asymmetric virtual ground gating and built-in read-assist schemes with inherent single-node event upset (SEU) preventive and self-correction capabilities and a high degree of robustness against multiple-node event upsets (MEUs) in the presence of more consumption area storage has been proposed. In order to investigate single/double upset injection circuit model using the structure of the T-connected pseudo resistors (TPRs) has been proposed. Also, based on the analytical-compact model, an equation for calculating the data-retention voltage (VDR) metric for the suggested bit-cell structure and an algorithm for facile estimate of VDR for other bit-cell architectures is presented. The results of extensive Monte-Carlo (MC) simulations to evaluate the proposed bit-cell indicate larger noise margins, acceptable yield, less sensitivity to process, voltage and temperature (PVT) variations, higher critical charge and consequence more robustness to soft errors with high reliability of data storage in standby mode in the presence of voltage conditions lower than the nominal power supply, and better results in other comprehensive figure of merits (FoMs) criteria compared to nanotechnology-based state-of-the-art radiation-hardened (rad-hard) bit-cell circuits with the same number of transistors in the 16 nm technology node. So, the proposed UPRHSE design can be a reasonable choice for applications that demands high stability, impact resistance to radiation particles and extremely low power in a radiation abundant environment with limited-energy sources. Finally, in order to use the suggested UPRHSE bit-cell in a real application with secure data transfer approach, the suggested structure is employed for storing. The results show the better performance of UPRHSE in terms of other comprehensive FoMs based on PSNR and MSSIM metric to evaluate the appropriate accuracy in pixel-by-pixel image compared to other well-known counterpart designs.

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