A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs

Design techniques for variability mitigation

“…Using pulsed-latch instead of Razor latch (Ernst et al, 2003;Lee et al, 2004) may lead to a faster decision about the correctness of propagated data. Augmenting clock skewing techniques (Andrade et al, 2009;Long et al, 2010) for time borrowing can preserve the sequence of pipeline without flushing. For power saving and thermal management, detecting the error rate is recommended to scale both frequency and voltage dynamically.…”

“…Because of variations, integrated circuits design should be based on the worst case timing principle as clock frequency should verify all of timing constraints under the worst conditions. A new compensation mechanism especially for environmental parameters fluctuation (voltage and temperature) was introduced in Andrade et al (2009). Complex microprocessor architecture was modelled by a structure of pipelined stages as shown in Figure 3.…”

“…Source: Andrade et al (2009) All registers are driven by a common clock signal. Because of the heterogeneity of the clock distribution network, a skew can affect the clock signals.…”

“…Equations (4) and (5) show the total processing time of the worst-case conditions for both conventional ( ) (Andrade et al, 2009). Where max(t p ) is the worst-case delay of any combinational logic between two registers, σ f is the standard deviation, K is a given number of standard deviations, and n is the number of stages (Andrade et al, 2009).…”

“…Where max(t p ) is the worst-case delay of any combinational logic between two registers, σ f is the standard deviation, K is a given number of standard deviations, and n is the number of stages (Andrade et al, 2009). The reduction of the propagation time for the whole pipeline chain is expressed by equation (6).…”