A New CMOS OP-AMP Design with an Improved Adaptive Biasing Circuitry

Abstract

This paper sets out a new technique for designing an operational amplifier (OP-AMP) using tanner EDA 1um FDSOI CMOS Technology. Fully Depleted Silicon on Insulator used for building integrated circuits to support the temperature changes, the proposed OP-AMP operates at 3.75V power supply and 70uA bias current using the proposed Adaptive Biasing Circuitry (ABC), which its devices operate at the weak inversion to allow low power dissipation of 0.62mW. The 0.064us settling time and 37.016V/μs slew rate parameters improved by the ABC technique, reducing the power dissipation by operating the ABC devices in weak inversion. The phase margin is more than 100 degrees for the DC gain of 13.97dB, which is a reasonable margin when temperature range increases.