In this work a reduced complexity chip-level linear SIC multiuser structure that is asymptotically equivalent to successive over-relaxation (SOR) iteration, which is known to outperform the conventional Gauss-Seidel iteration by an order of magnitude in terms of convergence speed, is proposed. The main advantage of the proposed scheme is its low computational complexity compared to other chip-level and symbol-level SIC schemes equivalent to successive over-relaxation (SOR) iteration. We study the convergence behaviour of the proposed scheme and prove that it converges if the relaxation factor is in the interval ]0, 2[. Simulation results are in excellent agreement with theory.